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From: David Gibson <david@gibson.dropbear.id.au>
To: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Cc: Nikunj Dadhania <nikunj.dadhania@gmail.com>,
	Bharata B Rao <bharata@linux.vnet.ibm.com>,
	qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 5/6] target-ppc: implement xxextractuw instruction
Date: Fri, 16 Dec 2016 15:19:36 +1100	[thread overview]
Message-ID: <20161216041936.GF12146@umbus.fritz.box> (raw)
In-Reply-To: <87d1guc32t.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me>

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On Wed, Dec 14, 2016 at 02:14:26PM +0530, Nikunj A Dadhania wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
> 
> > [ Unknown signature status ]
> > On Mon, Dec 12, 2016 at 09:31:11AM +0530, Nikunj Dadhania wrote:
> >> On 12 December 2016 at 06:00, David Gibson <david@gibson.dropbear.id.au> wrote:
> >> > On Fri, Dec 09, 2016 at 05:47:24PM +0530, Nikunj A Dadhania wrote:
> >> >> xxextractuw: VSX Vector Extract Unsigned Word
> >> >>
> >> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> >> >> +        tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0);         \
> >> >> +        tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0);         \
> >> >> +        return;                                                 \
> >> >
> >> > So, I know the architecture says it is undefined.  But since you're
> >> > testing for the bogus case anyway, why not turn this into an
> >> > exception. That seems like it would be more helpful for debugging the
> >> > guest than just setting the result to zero.  Or is this done to match
> >> > actual hardware behaviour?
> >> 
> >> I havent had a change to run on the real hardware, but on the system
> >> simulator, it happily
> >> returns extracted content even if UIMM > 12.
> >
> > Hm.  Returns what exactly?
> 
> So for LE case extracting from 15 returns following, basically its
> rounding up to 0.

> xxextractuw: 15 - ooTSET a si sihT
>                   ________ihTo____

Ok.  IIRC your implementation did not do this - it set the
"overflowed" bytes to 0 instead of wrapping round and taking them from
the other end of the input.  If think we should either match hardware
behaviour or simply trap here, rather than do something else.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2016-12-16  6:31 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-09 12:17 [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9 Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 1/6] target-ppc: implement lxvl instruction Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 2/6] target-ppc: implement lxvll instruction Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 3/6] target-ppc: implement stxvl instruction Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 4/6] target-ppc: implement stxvll instructions Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 5/6] target-ppc: implement xxextractuw instruction Nikunj A Dadhania
2016-12-12  0:30   ` David Gibson
2016-12-12  4:01     ` [Qemu-devel] [Qemu-ppc] " Nikunj Dadhania
2016-12-12  4:07       ` David Gibson
2016-12-14  8:44         ` Nikunj A Dadhania
2016-12-16  4:19           ` David Gibson [this message]
2016-12-19  4:25             ` Nikunj A Dadhania
2016-12-09 12:17 ` [Qemu-devel] [PATCH v2 6/6] target-ppc: implement xxinsertw instruction Nikunj A Dadhania
2016-12-12  0:32 ` [Qemu-devel] [PATCH v2 ppc-for-2.9 0/6] POWER9 TCG enablements - part9 David Gibson

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