From mboxrd@z Thu Jan  1 00:00:00 1970
From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
Subject: Re: Re: [PATCH 4/5] ARM: dts: sunxi: add dtsi file for
 V3s SoC
Date: Wed, 11 Jan 2017 11:56:32 +0800
Message-ID: <20170111065638.uW1SQ7Kq@smtp3m.mail.yandex.net>
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To: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>, linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>, linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
List-Id: linux-gpio@vger.kernel.org


2017=E5=B9=B41=E6=9C=8811=E6=97=A5 02:21=E4=BA=8E Maxime Ripard <maxime.rip=
ard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>=E5=86=99=E9=81=93=EF=BC=9A
>
> On Tue, Jan 03, 2017 at 11:16:28PM +0800, Icenowy Zheng wrote:=20
> > + uart0_pins_a: uart0@0 {=20
> > + pins =3D "PB8", "PB9";=20
> > + function =3D "uart0";=20
> > + bias-pull-up;=20
>
> Why do you need a pullup here?=20

I think TX needs one, but RX do not need.

>
> Looks good otherwise.=20
>
> Thanks!=20
> Maxime=20
>
> --=20
> Maxime Ripard, Free Electrons=20
> Embedded Linux and Kernel engineering=20
> http://free-electrons.com=20
>
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