From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752371AbdARUse (ORCPT ); Wed, 18 Jan 2017 15:48:34 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:35664 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751455AbdARUsa (ORCPT ); Wed, 18 Jan 2017 15:48:30 -0500 From: afzal mohammed To: Russell King - ARM Linux Cc: Vladimir Murzin , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, afzal mohammed Subject: [PATCH 4/4] ARM: nommu: remove Hivecs configuration is asm Date: Thu, 19 Jan 2017 02:09:20 +0530 Message-Id: <20170118203920.6609-1-afzal.mohd.ma@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170118203525.6246-1-afzal.mohd.ma@gmail.com> References: <20170118203525.6246-1-afzal.mohd.ma@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that exception based address is handled dynamically for processors with CP15, remove Highvecs configuration in assembly. Signed-off-by: afzal mohammed --- arch/arm/kernel/head-nommu.S | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index 6b4eb27b8758..2e21e08de747 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -152,11 +152,6 @@ __after_proc_init: #ifdef CONFIG_CPU_ICACHE_DISABLE bic r0, r0, #CR_I #endif -#ifdef CONFIG_CPU_HIGH_VECTOR - orr r0, r0, #CR_V -#else - bic r0, r0, #CR_V -#endif mcr p15, 0, r0, c1, c0, 0 @ write control reg #elif defined (CONFIG_CPU_V7M) /* For V7M systems we want to modify the CCR similarly to the SCTLR */ -- 2.11.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: afzal.mohd.ma@gmail.com (afzal mohammed) Date: Thu, 19 Jan 2017 02:09:20 +0530 Subject: [PATCH 4/4] ARM: nommu: remove Hivecs configuration is asm In-Reply-To: <20170118203525.6246-1-afzal.mohd.ma@gmail.com> References: <20170118203525.6246-1-afzal.mohd.ma@gmail.com> Message-ID: <20170118203920.6609-1-afzal.mohd.ma@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Now that exception based address is handled dynamically for processors with CP15, remove Highvecs configuration in assembly. Signed-off-by: afzal mohammed --- arch/arm/kernel/head-nommu.S | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index 6b4eb27b8758..2e21e08de747 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -152,11 +152,6 @@ __after_proc_init: #ifdef CONFIG_CPU_ICACHE_DISABLE bic r0, r0, #CR_I #endif -#ifdef CONFIG_CPU_HIGH_VECTOR - orr r0, r0, #CR_V -#else - bic r0, r0, #CR_V -#endif mcr p15, 0, r0, c1, c0, 0 @ write control reg #elif defined (CONFIG_CPU_V7M) /* For V7M systems we want to modify the CCR similarly to the SCTLR */ -- 2.11.0