From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Brandt Subject: [PATCH v3 2/3] ARM: dts: r7s72100: add ostm to device tree Date: Mon, 23 Jan 2017 08:55:19 -0500 Message-ID: <20170123135520.28834-3-chris.brandt@renesas.com> References: <20170123135520.28834-1-chris.brandt@renesas.com> Return-path: In-Reply-To: <20170123135520.28834-1-chris.brandt@renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org To: Simon Horman , Magnus Damm , Rob Herring , Mark Rutland , Russell King , Thomas Gleixner , Geert Uytterhoeven Cc: devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Brandt List-Id: devicetree@vger.kernel.org Signed-off-by: Chris Brandt --- v3: * changed ostm@xxx to timer@xxx * added power-domains to nodes v2: * wrap clock lines to avoid 80 char max * split into 2 separate channel nodes --- arch/arm/boot/dts/r7s72100.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index d5946df..74e684f 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -505,4 +505,22 @@ cap-sdio-irq; status = "disabled"; }; + + ostm0: timer@fcfec000 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec000 0x30>; + interrupts = ; + clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + ostm1: timer@fcfec400 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec400 0x30>; + interrupts = ; + clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; }; -- 2.10.1