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From: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Tony Cheng <tony.cheng-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 17/25] drm/amd/display: refactor clk_resync to avoid assertion
Date: Mon, 23 Jan 2017 09:36:05 -0500	[thread overview]
Message-ID: <20170123143613.15441-18-harry.wentland@amd.com> (raw)
In-Reply-To: <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>

From: Tony Cheng <tony.cheng@amd.com>

- not all DCE has PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE bit defined.

Change-Id: I4bf25deb134637c713ac5ee1eac786bafdc9eb4a
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
---
 .../gpu/drm/amd/display/dc/dce/dce_clock_source.c  | 57 ++++++++++++----------
 1 file changed, 30 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index a38172bdcb5e..78f43274a03a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -767,41 +767,44 @@ static void dce112_program_pixel_clk_resync(
 		enum dc_color_depth colordepth,
 		bool enable_ycbcr420)
 {
-	REG_UPDATE(PIXCLK_RESYNC_CNTL,
-			PHYPLLA_DCCG_DEEP_COLOR_CNTL, 0);
+	uint32_t deep_color_cntl = 0;
+	uint32_t double_rate_enable = 0;
+
 	/*
 	 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
 	 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
 	 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
 	 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
 	 */
-	if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
-		return;
+	if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
+		double_rate_enable = enable_ycbcr420 ? 1 : 0;
 
-	switch (colordepth) {
-	case COLOR_DEPTH_888:
-		REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
-				PHYPLLA_DCCG_DEEP_COLOR_CNTL, 0,
-				PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420);
-		break;
-	case COLOR_DEPTH_101010:
-		REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
-				PHYPLLA_DCCG_DEEP_COLOR_CNTL, 1,
-				PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420);
-		break;
-	case COLOR_DEPTH_121212:
-		REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
-				PHYPLLA_DCCG_DEEP_COLOR_CNTL, 2,
-				PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420);
-		break;
-	case COLOR_DEPTH_161616:
-		REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
-				PHYPLLA_DCCG_DEEP_COLOR_CNTL, 3,
-				PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420);
-		break;
-	default:
-		break;
+		switch (colordepth) {
+		case COLOR_DEPTH_888:
+			deep_color_cntl = 0;
+			break;
+		case COLOR_DEPTH_101010:
+			deep_color_cntl = 1;
+			break;
+		case COLOR_DEPTH_121212:
+			deep_color_cntl = 2;
+			break;
+		case COLOR_DEPTH_161616:
+			deep_color_cntl = 3;
+			break;
+		default:
+			break;
+		}
 	}
+
+	if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE)
+		REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
+				PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl,
+				PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable);
+	else
+		REG_UPDATE(PIXCLK_RESYNC_CNTL,
+				PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl);
+
 }
 
 static bool dce110_program_pix_clk(
-- 
2.9.3

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  parent reply	other threads:[~2017-01-23 14:36 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-23 14:35 [PATCH 00/25] DC Patches Jan 23, 2017 Harry Wentland
     [not found] ` <20170123143613.15441-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2017-01-23 14:35   ` [PATCH 01/25] drm/amd/display: Null check clock source Harry Wentland
2017-01-23 14:35   ` [PATCH 02/25] drm/amd/display: Output Transfer Function Regamma Refactor Harry Wentland
2017-01-23 14:35   ` [PATCH 03/25] drm/amd/display: Disable Modules at Runtime Harry Wentland
2017-01-23 14:35   ` [PATCH 04/25] drm/amd/display: Fixing some fallout from dc_target removal Harry Wentland
2017-01-23 14:35   ` [PATCH 05/25] drm/amd/display: No audio output heard from DP panel Harry Wentland
2017-01-23 14:35   ` [PATCH 06/25] drm/amd/display: Use pflip prepare and submit parts (v2) Harry Wentland
2017-01-23 14:35   ` [PATCH 07/25] drm/amd/display: mode change without breaking unaffected streams Harry Wentland
2017-01-23 14:35   ` [PATCH 08/25] drm/amd/display: assert if mask is 0 in set_reg_field_value_ex Harry Wentland
2017-01-23 14:35   ` [PATCH 09/25] drm/amd/display: remove un-used defines and dead code Harry Wentland
2017-01-23 14:35   ` [PATCH 10/25] drm/amd/display: remove hw_crtc_timing Harry Wentland
2017-01-23 14:35   ` [PATCH 11/25] drm/amd/display: remove hw_info_frame Harry Wentland
2017-01-23 14:36   ` [PATCH 12/25] drm/amd/display: remove SIGNAL_TYPE_WIRELESS Harry Wentland
2017-01-23 14:36   ` [PATCH 13/25] drm/amd/display: remove dead code Harry Wentland
2017-01-23 14:36   ` [PATCH 14/25] drm/amd/display: remove calculate_adjustments in conversion.h Harry Wentland
2017-01-23 14:36   ` [PATCH 15/25] drm/amd/display: Set default degamma to sRGB instead of bypass Harry Wentland
2017-01-23 14:36   ` [PATCH 16/25] drm/amd/display: HDR Enablement For Applications Harry Wentland
2017-01-23 14:36   ` Harry Wentland [this message]
2017-01-23 14:36   ` [PATCH 18/25] drm/amd/display: Remove meta_pitch Harry Wentland
2017-01-23 14:36   ` [PATCH 19/25] drm/amd/display: rename BGRA8888 to ABGR8888 Harry Wentland
2017-01-23 14:36   ` [PATCH 20/25] drm/amd/display: Fix missing conditions in hw sequencer Harry Wentland
2017-01-23 14:36   ` [PATCH 21/25] drm/amd/display: Add missing MI masks Harry Wentland
2017-01-23 14:36   ` [PATCH 22/25] drm/amd/display: Add interrupt entries for VBLANK isr Harry Wentland
     [not found]     ` <20170123143613.15441-23-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2017-01-23 17:43       ` Alex Deucher
2017-01-23 14:36   ` [PATCH 23/25] drm/amd/display: Register on VLBLANK ISR Harry Wentland
2017-01-23 14:36   ` [PATCH 24/25] drm/amd/display: Clean index in irq init loop Harry Wentland
2017-01-23 14:36   ` [PATCH 25/25] drm/amd/display: add missing dcc update on flip call Harry Wentland

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