From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Mon, 23 Jan 2017 15:55:57 +0100 Subject: [U-Boot] [PATCH v2] spi: ich: Configure SPI BIOS parameters In-Reply-To: <20170120142618.19119-1-sr@denx.de> References: <20170120142618.19119-1-sr@denx.de> Message-ID: <20170123145557.24415-1-sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Without configuring these registers in the SPI controller, the Linux MTD device driver is not able to correctly read/write to the SPI NOR chip at all. In fact, the chip is not detected at all. Signed-off-by: Stefan Roese Cc: Bin Meng Cc: Simon Glass Cc: Jagan Teki --- v2: - Moved code into the ICH SPI driver as suggested by Simon and Bin drivers/spi/ich.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index caf0103dc3..586b4e9024 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -18,6 +18,39 @@ #include "ich.h" +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) + DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG_TRACE @@ -111,6 +144,17 @@ static int ich9_can_do_33mhz(struct udevice *dev) return speed == 1; } +/* + * Configure SPI controller so that the Linux MTD driver can fully + * access the SPI NOR chip + */ +static void spi_controller_config(struct ich_spi_priv *ctlr) +{ + ich_writew(ctlr, SPI_OPTYPE, ctlr->optype); + ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu); + ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32)); +} + static int ich_init_controller(struct udevice *dev, struct ich_spi_platdata *plat, struct ich_spi_priv *ctlr) @@ -172,6 +216,13 @@ static int ich_init_controller(struct udevice *dev, ich_set_bbar(ctlr, 0); + /* + * Configure the SPI-NOR controller in a way that the Linux + * MTD SPI-NOR device driver has full read-write access to + * the SPI-NOR chips + */ + spi_controller_config(ctlr); + return 0; } -- 2.11.0