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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Subject: [PATCH v3 4/8] drm/i915: Only run execlist context-switch handler after an interrupt
Date: Tue, 24 Jan 2017 11:00:05 +0000	[thread overview]
Message-ID: <20170124110009.28947-4-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20170124110009.28947-1-chris@chris-wilson.co.uk>

Mark when we run the execlist tasklet following the interrupt, so we
don't probe a potentially uninitialised register when submitting the
contexts multiple times before the hardware responds.

v2: Use a shared engine->irq_posted

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com
---
 drivers/gpu/drm/i915/i915_irq.c         | 7 +++++--
 drivers/gpu/drm/i915/intel_lrc.c        | 3 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7e087c344265..3f3c9082b0f8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1349,8 +1349,11 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
 {
 	if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
 		notify_ring(engine);
-	if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
-		tasklet_schedule(&engine->irq_tasklet);
+
+	if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
+		set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+		tasklet_hi_schedule(&engine->irq_tasklet);
+	}
 }
 
 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9896027880ea..7db9c49450f9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -564,7 +564,7 @@ static void intel_lrc_irq_handler(unsigned long data)
 
 	intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
 
-	if (!execlists_elsp_idle(engine)) {
+	while (__test_and_clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
 		u32 __iomem *csb_mmio =
 			dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
 		u32 __iomem *buf =
@@ -1297,6 +1297,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
 	DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
 
 	/* After a GPU reset, we may have requests to replay */
+	__clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
 	if (!execlists_elsp_idle(engine)) {
 		engine->execlist_port[0].count = 0;
 		engine->execlist_port[1].count = 0;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index a9ea84ea3155..8e872730f8eb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -213,6 +213,7 @@ struct intel_engine_cs {
 
 	unsigned long irq_posted;
 #define ENGINE_IRQ_BREADCRUMB 0
+#define ENGINE_IRQ_EXECLIST 1
 
 	/* Rather than have every client wait upon all user interrupts,
 	 * with the herd waking after every interrupt and each doing the
-- 
2.11.0

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  parent reply	other threads:[~2017-01-24 11:00 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-24 11:00 [PATCH v3 1/8] drm/i915: Assert that we don't submit to execlists whilst a preempt is pending Chris Wilson
2017-01-24 11:00 ` [PATCH v3 2/8] drm/i915: Only disable execlist preemption for the duration of the request Chris Wilson
2017-01-24 11:00 ` [PATCH v3 3/8] drm/i915: Move breadcrumbs irq_posted up a level to engine Chris Wilson
2017-01-24 15:18   ` [PATCH v4] " Chris Wilson
2017-01-24 15:45     ` Mika Kuoppala
2017-01-24 11:00 ` Chris Wilson [this message]
2017-01-24 15:20   ` [PATCH v4] drm/i915: Only run execlist context-switch handler after an interrupt Chris Wilson
2017-01-24 15:46     ` Mika Kuoppala
2017-01-24 11:00 ` [PATCH v3 5/8] drm/i915: Skip the execlists CSB scan and rewrite if the ring is untouched Chris Wilson
2017-01-24 11:00 ` [PATCH v3 6/8] drm/i915: Only attempt to pass the first request to execlists Chris Wilson
2017-01-24 15:51   ` Mika Kuoppala
2017-01-24 11:00 ` [PATCH v3 7/8] drm/i915: Dequeue execlists on a new request if any port is available Chris Wilson
2017-01-24 11:00 ` [PATCH v3 8/8] drm/i915: Emit dma-fence (and execlists submit) first from signaler Chris Wilson
2017-01-24 11:54 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/8] drm/i915: Assert that we don't submit to execlists whilst a preempt is pending Patchwork
2017-01-24 15:54 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/8] drm/i915: Assert that we don't submit to execlists whilst a preempt is pending (rev3) Patchwork
2017-01-24 16:06   ` Chris Wilson

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