From: Stafford Horne <shorne@gmail.com>
To: Richard Henderson <rth@twiddle.net>
Cc: Jia Liu <proljc@gmail.com>,
qemu-devel@nongnu.org, openrisc@lists.librecores.org
Subject: Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers
Date: Fri, 27 Jan 2017 07:01:26 +0900 [thread overview]
Message-ID: <20170126220126.GC21641@lianli.shorne-pla.net> (raw)
In-Reply-To: <ddb9c656-aa3e-5d90-c8fc-0058af5b603b@twiddle.net>
On Thu, Jan 26, 2017 at 09:26:55AM -0800, Richard Henderson wrote:
> On 01/26/2017 05:12 AM, Stafford Horne wrote:
> > I just sent you a mail with a link to my kernel for download.
> >
> > One thing I noticed is you passed '-append console=ttyS0' I think that
> > does nothing on openrisc since as far as I know openrisc only gets boot
> > params from the device tree file. I tried with and without it and got no
> > differences.
>
> That was just reflex, wondering where the output went.
>
> > Another thing, I am using a 'late' version of gcc built with musl cross [1]
> > , I dont think it would make a difference, but maybe?
>
> I think that's likely the difference. I can indeed boot your kernel.
OK, you can try to build with the musl-cross link I sent you.
https://github.com/openrisc/musl-cross/tree/or1k
Also, for the linux kernel crosstool project I am working on getting
their toolchain updated to support l.swa/l.lwa. I have posted some
binaries here (but no libc needed for the kernel):
http://shorne.noip.me/crosstool/files/bin/x86_64/5.4.0/
The official ones are all here (below), but much too old to support openrisc
modern instructions.
https://www.kernel.org/pub/tools/crosstool/
-Stafford
WARNING: multiple messages have this Message-ID (diff)
From: Stafford Horne <shorne@gmail.com>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers
Date: Fri, 27 Jan 2017 07:01:26 +0900 [thread overview]
Message-ID: <20170126220126.GC21641@lianli.shorne-pla.net> (raw)
In-Reply-To: <ddb9c656-aa3e-5d90-c8fc-0058af5b603b@twiddle.net>
On Thu, Jan 26, 2017 at 09:26:55AM -0800, Richard Henderson wrote:
> On 01/26/2017 05:12 AM, Stafford Horne wrote:
> > I just sent you a mail with a link to my kernel for download.
> >
> > One thing I noticed is you passed '-append console=ttyS0' I think that
> > does nothing on openrisc since as far as I know openrisc only gets boot
> > params from the device tree file. I tried with and without it and got no
> > differences.
>
> That was just reflex, wondering where the output went.
>
> > Another thing, I am using a 'late' version of gcc built with musl cross [1]
> > , I dont think it would make a difference, but maybe?
>
> I think that's likely the difference. I can indeed boot your kernel.
OK, you can try to build with the musl-cross link I sent you.
https://github.com/openrisc/musl-cross/tree/or1k
Also, for the linux kernel crosstool project I am working on getting
their toolchain updated to support l.swa/l.lwa. I have posted some
binaries here (but no libc needed for the kernel):
http://shorne.noip.me/crosstool/files/bin/x86_64/5.4.0/
The official ones are all here (below), but much too old to support openrisc
modern instructions.
https://www.kernel.org/pub/tools/crosstool/
-Stafford
next prev parent reply other threads:[~2017-01-26 22:01 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-13 21:57 [OpenRISC] [PATCH] target-openrisc: Fix exception handling status registers Stafford Horne
2017-01-13 22:02 ` Stafford Horne
2017-01-14 4:29 ` Jia Liu
2017-01-14 8:04 ` [Qemu-devel] " Stafford Horne
2017-01-14 8:04 ` [OpenRISC] " Stafford Horne
2017-01-20 16:39 ` [Qemu-devel] " Stafford Horne
2017-01-20 16:39 ` [OpenRISC] " Stafford Horne
2017-01-23 18:08 ` [Qemu-devel] " Richard Henderson
2017-01-23 18:08 ` [OpenRISC] " Richard Henderson
2017-01-24 10:26 ` Stafford Horne
2017-01-24 10:26 ` [OpenRISC] " Stafford Horne
2017-01-24 18:32 ` Richard Henderson
2017-01-24 18:32 ` [OpenRISC] " Richard Henderson
2017-01-25 12:34 ` Stafford Horne
2017-01-25 12:34 ` [OpenRISC] " Stafford Horne
2017-01-25 17:27 ` Richard Henderson
2017-01-25 17:27 ` [OpenRISC] " Richard Henderson
2017-01-26 13:12 ` Stafford Horne
2017-01-26 13:12 ` [OpenRISC] " Stafford Horne
2017-01-26 17:26 ` Richard Henderson
2017-01-26 17:26 ` [OpenRISC] " Richard Henderson
2017-01-26 22:01 ` Stafford Horne [this message]
2017-01-26 22:01 ` Stafford Horne
2017-02-01 10:04 ` Stafford Horne
2017-02-01 10:04 ` [OpenRISC] " Stafford Horne
2017-02-01 18:15 ` Richard Henderson
2017-02-01 18:15 ` [OpenRISC] " Richard Henderson
2017-02-02 14:34 ` Stafford Horne
2017-02-02 14:34 ` [OpenRISC] " Stafford Horne
2017-02-03 15:14 ` Stafford Horne
2017-02-03 15:14 ` [OpenRISC] " Stafford Horne
2017-02-07 2:36 ` Richard Henderson
2017-02-07 2:36 ` [OpenRISC] " Richard Henderson
2017-02-06 20:44 ` Richard Henderson
2017-02-07 0:31 ` Stafford Horne
2017-02-07 5:48 ` Richard Henderson
2017-02-07 5:53 ` Richard Henderson
2017-02-07 5:53 ` [OpenRISC] " Richard Henderson
2017-02-08 14:01 ` Stafford Horne
2017-02-08 14:01 ` [OpenRISC] " Stafford Horne
2017-02-08 16:38 ` Stafford Horne
2017-02-08 16:38 ` [OpenRISC] " Stafford Horne
2017-02-08 20:38 ` Richard Henderson
2017-02-08 20:38 ` [OpenRISC] " Richard Henderson
2017-01-13 22:00 Stafford Horne
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