From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751603AbdA2OsE (ORCPT ); Sun, 29 Jan 2017 09:48:04 -0500 Received: from dougal.metanate.com ([90.155.101.14]:25186 "EHLO metanate.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751529AbdA2OsA (ORCPT ); Sun, 29 Jan 2017 09:48:00 -0500 From: John Keeping To: Mark Yao Cc: Chris Zhong , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, John Keeping Subject: [PATCH v3 13/24] drm/rockchip: dw-mipi-dsi: fix escape clock rate Date: Sun, 29 Jan 2017 13:24:33 +0000 Message-Id: <20170129132444.25251-14-john@metanate.com> X-Mailer: git-send-email 2.11.0.197.gb556de5.dirty In-Reply-To: <20170129132444.25251-1-john@metanate.com> References: <20170129132444.25251-1-john@metanate.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This clock rate is derived from the PHY PLL, so it should be calculated dynamically. Use the same calculation as the vendor kernel to derive the escape clock speed. Signed-off-by: John Keeping Reviewed-by: Chris Zhong --- v3: - Improve the commit message a bit - Add Chris' Reviewed-by Unchanged in v2 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 290282e86d16..c2e0ba96e0a0 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -710,11 +710,13 @@ static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) { + u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; + dsi_write(dsi, DSI_PWR_UP, RESET); dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK | PHY_RSTZ | PHY_SHUTDOWNZ); dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | - TX_ESC_CLK_DIVIDSION(7)); + TX_ESC_CLK_DIVIDSION(esc_clk_division)); } static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, -- 2.11.0.197.gb556de5.dirty From mboxrd@z Thu Jan 1 00:00:00 1970 From: John Keeping Subject: [PATCH v3 13/24] drm/rockchip: dw-mipi-dsi: fix escape clock rate Date: Sun, 29 Jan 2017 13:24:33 +0000 Message-ID: <20170129132444.25251-14-john@metanate.com> References: <20170129132444.25251-1-john@metanate.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20170129132444.25251-1-john@metanate.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Mark Yao Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org List-Id: linux-rockchip.vger.kernel.org VGhpcyBjbG9jayByYXRlIGlzIGRlcml2ZWQgZnJvbSB0aGUgUEhZIFBMTCwgc28gaXQgc2hvdWxk IGJlIGNhbGN1bGF0ZWQKZHluYW1pY2FsbHkuICBVc2UgdGhlIHNhbWUgY2FsY3VsYXRpb24gYXMg dGhlIHZlbmRvciBrZXJuZWwgdG8gZGVyaXZlCnRoZSBlc2NhcGUgY2xvY2sgc3BlZWQuCgpTaWdu ZWQtb2ZmLWJ5OiBKb2huIEtlZXBpbmcgPGpvaG5AbWV0YW5hdGUuY29tPgpSZXZpZXdlZC1ieTog Q2hyaXMgWmhvbmcgPHp5d0Byb2NrLWNoaXBzLmNvbT4KLS0tCnYzOgotIEltcHJvdmUgdGhlIGNv bW1pdCBtZXNzYWdlIGEgYml0Ci0gQWRkIENocmlzJyBSZXZpZXdlZC1ieQpVbmNoYW5nZWQgaW4g djIKCiBkcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvZHctbWlwaS1kc2kuYyB8IDQgKysrLQogMSBm aWxlIGNoYW5nZWQsIDMgaW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbigtKQoKZGlmZiAtLWdpdCBh L2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jIGIvZHJpdmVycy9ncHUvZHJt L3JvY2tjaGlwL2R3LW1pcGktZHNpLmMKaW5kZXggMjkwMjgyZTg2ZDE2Li5jMmUwYmE5NmUwYTAg MTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jCisrKyBi L2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jCkBAIC03MTAsMTEgKzcxMCwx MyBAQCBzdGF0aWMgdm9pZCBkd19taXBpX2RzaV9kaXNhYmxlKHN0cnVjdCBkd19taXBpX2RzaSAq ZHNpKQogCiBzdGF0aWMgdm9pZCBkd19taXBpX2RzaV9pbml0KHN0cnVjdCBkd19taXBpX2RzaSAq ZHNpKQogeworCXUzMiBlc2NfY2xrX2RpdmlzaW9uID0gKGRzaS0+bGFuZV9tYnBzID4+IDMpIC8g MjAgKyAxOworCiAJZHNpX3dyaXRlKGRzaSwgRFNJX1BXUl9VUCwgUkVTRVQpOwogCWRzaV93cml0 ZShkc2ksIERTSV9QSFlfUlNUWiwgUEhZX0RJU0ZPUkNFUExMIHwgUEhZX0RJU0FCTEVDTEsKIAkJ ICB8IFBIWV9SU1RaIHwgUEhZX1NIVVRET1dOWik7CiAJZHNpX3dyaXRlKGRzaSwgRFNJX0NMS01H Ul9DRkcsIFRPX0NMS19ESVZJRFNJT04oMTApIHwKLQkJICBUWF9FU0NfQ0xLX0RJVklEU0lPTig3 KSk7CisJCSAgVFhfRVNDX0NMS19ESVZJRFNJT04oZXNjX2Nsa19kaXZpc2lvbikpOwogfQogCiBz dGF0aWMgdm9pZCBkd19taXBpX2RzaV9kcGlfY29uZmlnKHN0cnVjdCBkd19taXBpX2RzaSAqZHNp LAotLSAKMi4xMS4wLjE5Ny5nYjU1NmRlNS5kaXJ0eQoKX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxA bGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxt YW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: john@metanate.com (John Keeping) Date: Sun, 29 Jan 2017 13:24:33 +0000 Subject: [PATCH v3 13/24] drm/rockchip: dw-mipi-dsi: fix escape clock rate In-Reply-To: <20170129132444.25251-1-john@metanate.com> References: <20170129132444.25251-1-john@metanate.com> Message-ID: <20170129132444.25251-14-john@metanate.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This clock rate is derived from the PHY PLL, so it should be calculated dynamically. Use the same calculation as the vendor kernel to derive the escape clock speed. Signed-off-by: John Keeping Reviewed-by: Chris Zhong --- v3: - Improve the commit message a bit - Add Chris' Reviewed-by Unchanged in v2 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 290282e86d16..c2e0ba96e0a0 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -710,11 +710,13 @@ static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) { + u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; + dsi_write(dsi, DSI_PWR_UP, RESET); dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK | PHY_RSTZ | PHY_SHUTDOWNZ); dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | - TX_ESC_CLK_DIVIDSION(7)); + TX_ESC_CLK_DIVIDSION(esc_clk_division)); } static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, -- 2.11.0.197.gb556de5.dirty