From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@armlinux.org.uk (Russell King - ARM Linux) Date: Mon, 30 Jan 2017 15:19:33 +0000 Subject: [PATCH 06/10] soc/qbman: Add ARM equivalent for flush_dcache_range() In-Reply-To: References: <1484779180-1344-1-git-send-email-roy.pledge@nxp.com> <5414359.8GMja3pNrI@wuerfel> Message-ID: <20170130151933.GA27312@n2100.armlinux.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Jan 27, 2017 at 05:41:10PM +0100, Arnd Bergmann wrote: > On Thu, Jan 26, 2017 at 6:08 AM, Scott Wood wrote: > > And even if we did all that, there would still be other manual cache > > manipulation left in this driver, to deal with its cacheable register > > interface. > > I thought we had concluded that "cacheable register" is something > that cannot work reliably on ARM at all when this came up before. > Any updates on that? There's a big comment in arch/arm/include/asm/io.h which explains everything. Nothing there is likely to change. -- RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net.