From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932421AbdA3P7T (ORCPT ); Mon, 30 Jan 2017 10:59:19 -0500 Received: from mail.skyhub.de ([78.46.96.112]:35554 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932374AbdA3P7D (ORCPT ); Mon, 30 Jan 2017 10:59:03 -0500 Date: Mon, 30 Jan 2017 16:58:39 +0100 From: Borislav Petkov To: Thomas Gleixner , Henning Schild Cc: LKML , Ingo Molnar , Peter Zijlstra , Yinghai Lu Subject: Re: [3/8] x86/tsc: Store and check TSC ADJUST MSR Message-ID: <20170130155839.t6ku6kbqyegry7pm@pd.tnic> References: <20161119134017.655323776@linutronix.de> <20170127143632.4f56d927@md1em3qc> <20170130131301.7ddae08d@md1em3qc> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20161014 (1.7.1) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 30, 2017 at 02:04:46PM +0100, Thomas Gleixner wrote: > > The AMD-Manual from 12/16 does not mention that MSR. I do not have > > access to an AMD machine. But i can only assume that bigger machines > > also suffer from async TSCs and basically all fall back to HPET. > > Borislav? So far, all AMD machines starting from Barcelona (F10h) onwards should have a stable TSC. If you've seen some discrepancies, make sure to let us know. The bigger machines I have access to are all ok wrt synchronized TSCs but I won't be surprised if someone proves me wrong. Of course, if dumb firmware decides to fiddle with the TSC, then dumb firmware should be fixed. Wrt TSC adjust MSR, it should be probably best to take this up with AMD engineering. HTH. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.