From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752130AbdAaToh (ORCPT ); Tue, 31 Jan 2017 14:44:37 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:36065 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751652AbdAaToS (ORCPT ); Tue, 31 Jan 2017 14:44:18 -0500 Date: Tue, 31 Jan 2017 20:35:25 +0100 From: Daniel Vetter To: Eric Anholt Cc: Florian Fainelli , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , dri-devel@lists.freedesktop.org, Thierry Reding , Stephen Warren , Lee Jones , linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 04/11] drm/vc4: Set up SCALER_DISPCTRL at boot. Message-ID: <20170131193525.bjwzmsy74ax4wyy7@phenom.ffwll.local> Mail-Followup-To: Eric Anholt , Florian Fainelli , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , dri-devel@lists.freedesktop.org, Thierry Reding , Stephen Warren , Lee Jones , linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20161214194621.16499-1-eric@anholt.net> <20161214194621.16499-5-eric@anholt.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161214194621.16499-5-eric@anholt.net> X-Operating-System: Linux phenom 4.8.0-1-amd64 User-Agent: NeoMutt/20161126 (1.7.1) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 14, 2016 at 11:46:14AM -0800, Eric Anholt wrote: > We want the HVS on, obviously, and we also want DSP3 (PV1's source) to > be muxed from HVS channel 2 like we expect in vc4_crtc.c. The > firmware wasn't setting the DSP3 mux up when both the LCD and HDMI > were disabled. > > Signed-off-by: Eric Anholt Yeah, the hvs magic is checked with require_hvs_enable. And the hvs channel 2 for pv 1 seems to check out too, though I wonder why you don't just set up all the mappings unconditionally. Anyway, looks reasonable. Acked-by: Daniel Vetter > --- > drivers/gpu/drm/vc4/vc4_hvs.c | 14 ++++++++++++++ > drivers/gpu/drm/vc4/vc4_regs.h | 3 +++ > 2 files changed, 17 insertions(+) > > diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c > index 6fbab1c82cb1..fc68b1b4da52 100644 > --- a/drivers/gpu/drm/vc4/vc4_hvs.c > +++ b/drivers/gpu/drm/vc4/vc4_hvs.c > @@ -170,6 +170,7 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) > struct vc4_dev *vc4 = drm->dev_private; > struct vc4_hvs *hvs = NULL; > int ret; > + u32 dispctrl; > > hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL); > if (!hvs) > @@ -211,6 +212,19 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) > return ret; > > vc4->hvs = hvs; > + > + dispctrl = HVS_READ(SCALER_DISPCTRL); > + > + dispctrl |= SCALER_DISPCTRL_ENABLE; > + > + /* Set DSP3 (PV1) to use HVS channel 2, which would otherwise > + * be unused. > + */ > + dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK; > + dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX); > + > + HVS_WRITE(SCALER_DISPCTRL, dispctrl); > + > return 0; > } > > diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h > index 39f6886b2410..b3b297fba709 100644 > --- a/drivers/gpu/drm/vc4/vc4_regs.h > +++ b/drivers/gpu/drm/vc4/vc4_regs.h > @@ -244,6 +244,9 @@ > # define SCALER_DISPCTRL_ENABLE BIT(31) > # define SCALER_DISPCTRL_DSP2EISLUR BIT(15) > # define SCALER_DISPCTRL_DSP1EISLUR BIT(14) > +# define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18) > +# define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18 > + > /* Enables Display 0 short line and underrun contribution to > * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are > * always enabled. > -- > 2.11.0 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From mboxrd@z Thu Jan 1 00:00:00 1970 From: daniel@ffwll.ch (Daniel Vetter) Date: Tue, 31 Jan 2017 20:35:25 +0100 Subject: [PATCH 04/11] drm/vc4: Set up SCALER_DISPCTRL at boot. In-Reply-To: <20161214194621.16499-5-eric@anholt.net> References: <20161214194621.16499-1-eric@anholt.net> <20161214194621.16499-5-eric@anholt.net> Message-ID: <20170131193525.bjwzmsy74ax4wyy7@phenom.ffwll.local> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Dec 14, 2016 at 11:46:14AM -0800, Eric Anholt wrote: > We want the HVS on, obviously, and we also want DSP3 (PV1's source) to > be muxed from HVS channel 2 like we expect in vc4_crtc.c. The > firmware wasn't setting the DSP3 mux up when both the LCD and HDMI > were disabled. > > Signed-off-by: Eric Anholt Yeah, the hvs magic is checked with require_hvs_enable. And the hvs channel 2 for pv 1 seems to check out too, though I wonder why you don't just set up all the mappings unconditionally. Anyway, looks reasonable. Acked-by: Daniel Vetter > --- > drivers/gpu/drm/vc4/vc4_hvs.c | 14 ++++++++++++++ > drivers/gpu/drm/vc4/vc4_regs.h | 3 +++ > 2 files changed, 17 insertions(+) > > diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c > index 6fbab1c82cb1..fc68b1b4da52 100644 > --- a/drivers/gpu/drm/vc4/vc4_hvs.c > +++ b/drivers/gpu/drm/vc4/vc4_hvs.c > @@ -170,6 +170,7 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) > struct vc4_dev *vc4 = drm->dev_private; > struct vc4_hvs *hvs = NULL; > int ret; > + u32 dispctrl; > > hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL); > if (!hvs) > @@ -211,6 +212,19 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) > return ret; > > vc4->hvs = hvs; > + > + dispctrl = HVS_READ(SCALER_DISPCTRL); > + > + dispctrl |= SCALER_DISPCTRL_ENABLE; > + > + /* Set DSP3 (PV1) to use HVS channel 2, which would otherwise > + * be unused. > + */ > + dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK; > + dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX); > + > + HVS_WRITE(SCALER_DISPCTRL, dispctrl); > + > return 0; > } > > diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h > index 39f6886b2410..b3b297fba709 100644 > --- a/drivers/gpu/drm/vc4/vc4_regs.h > +++ b/drivers/gpu/drm/vc4/vc4_regs.h > @@ -244,6 +244,9 @@ > # define SCALER_DISPCTRL_ENABLE BIT(31) > # define SCALER_DISPCTRL_DSP2EISLUR BIT(15) > # define SCALER_DISPCTRL_DSP1EISLUR BIT(14) > +# define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18) > +# define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18 > + > /* Enables Display 0 short line and underrun contribution to > * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are > * always enabled. > -- > 2.11.0 > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 04/11] drm/vc4: Set up SCALER_DISPCTRL at boot. Date: Tue, 31 Jan 2017 20:35:25 +0100 Message-ID: <20170131193525.bjwzmsy74ax4wyy7@phenom.ffwll.local> References: <20161214194621.16499-1-eric@anholt.net> <20161214194621.16499-5-eric@anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id B37A36E705 for ; Tue, 31 Jan 2017 19:35:30 +0000 (UTC) Received: by mail-wm0-x243.google.com with SMTP id v77so438971wmv.0 for ; Tue, 31 Jan 2017 11:35:30 -0800 (PST) Content-Disposition: inline In-Reply-To: <20161214194621.16499-5-eric@anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Eric Anholt Cc: Mark Rutland , Florian Fainelli , Stephen Warren , Michael Turquette , Lee Jones , Stephen Boyd , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: dri-devel@lists.freedesktop.org T24gV2VkLCBEZWMgMTQsIDIwMTYgYXQgMTE6NDY6MTRBTSAtMDgwMCwgRXJpYyBBbmhvbHQgd3Jv dGU6Cj4gV2Ugd2FudCB0aGUgSFZTIG9uLCBvYnZpb3VzbHksIGFuZCB3ZSBhbHNvIHdhbnQgRFNQ MyAoUFYxJ3Mgc291cmNlKSB0bwo+IGJlIG11eGVkIGZyb20gSFZTIGNoYW5uZWwgMiBsaWtlIHdl IGV4cGVjdCBpbiB2YzRfY3J0Yy5jLiAgVGhlCj4gZmlybXdhcmUgd2Fzbid0IHNldHRpbmcgdGhl IERTUDMgbXV4IHVwIHdoZW4gYm90aCB0aGUgTENEIGFuZCBIRE1JCj4gd2VyZSBkaXNhYmxlZC4K PiAKPiBTaWduZWQtb2ZmLWJ5OiBFcmljIEFuaG9sdCA8ZXJpY0BhbmhvbHQubmV0PgoKWWVhaCwg dGhlIGh2cyBtYWdpYyBpcyBjaGVja2VkIHdpdGggcmVxdWlyZV9odnNfZW5hYmxlLiBBbmQgdGhl IGh2cwpjaGFubmVsIDIgZm9yIHB2IDEgc2VlbXMgdG8gY2hlY2sgb3V0IHRvbywgdGhvdWdoIEkg d29uZGVyIHdoeSB5b3UgZG9uJ3QKanVzdCBzZXQgdXAgYWxsIHRoZSBtYXBwaW5ncyB1bmNvbmRp dGlvbmFsbHkuIEFueXdheSwgbG9va3MgcmVhc29uYWJsZS4KCkFja2VkLWJ5OiBEYW5pZWwgVmV0 dGVyIDxkYW5pZWwudmV0dGVyQGZmd2xsLmNoPgo+IC0tLQo+ICBkcml2ZXJzL2dwdS9kcm0vdmM0 L3ZjNF9odnMuYyAgfCAxNCArKysrKysrKysrKysrKwo+ICBkcml2ZXJzL2dwdS9kcm0vdmM0L3Zj NF9yZWdzLmggfCAgMyArKysKPiAgMiBmaWxlcyBjaGFuZ2VkLCAxNyBpbnNlcnRpb25zKCspCj4g Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS92YzQvdmM0X2h2cy5jIGIvZHJpdmVycy9n cHUvZHJtL3ZjNC92YzRfaHZzLmMKPiBpbmRleCA2ZmJhYjFjODJjYjEuLmZjNjhiMWI0ZGE1MiAx MDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vdmM0L3ZjNF9odnMuYwo+ICsrKyBiL2RyaXZl cnMvZ3B1L2RybS92YzQvdmM0X2h2cy5jCj4gQEAgLTE3MCw2ICsxNzAsNyBAQCBzdGF0aWMgaW50 IHZjNF9odnNfYmluZChzdHJ1Y3QgZGV2aWNlICpkZXYsIHN0cnVjdCBkZXZpY2UgKm1hc3Rlciwg dm9pZCAqZGF0YSkKPiAgCXN0cnVjdCB2YzRfZGV2ICp2YzQgPSBkcm0tPmRldl9wcml2YXRlOwo+ ICAJc3RydWN0IHZjNF9odnMgKmh2cyA9IE5VTEw7Cj4gIAlpbnQgcmV0Owo+ICsJdTMyIGRpc3Bj dHJsOwo+ICAKPiAgCWh2cyA9IGRldm1fa3phbGxvYygmcGRldi0+ZGV2LCBzaXplb2YoKmh2cyks IEdGUF9LRVJORUwpOwo+ICAJaWYgKCFodnMpCj4gQEAgLTIxMSw2ICsyMTIsMTkgQEAgc3RhdGlj IGludCB2YzRfaHZzX2JpbmQoc3RydWN0IGRldmljZSAqZGV2LCBzdHJ1Y3QgZGV2aWNlICptYXN0 ZXIsIHZvaWQgKmRhdGEpCj4gIAkJcmV0dXJuIHJldDsKPiAgCj4gIAl2YzQtPmh2cyA9IGh2czsK PiArCj4gKwlkaXNwY3RybCA9IEhWU19SRUFEKFNDQUxFUl9ESVNQQ1RSTCk7Cj4gKwo+ICsJZGlz cGN0cmwgfD0gU0NBTEVSX0RJU1BDVFJMX0VOQUJMRTsKPiArCj4gKwkvKiBTZXQgRFNQMyAoUFYx KSB0byB1c2UgSFZTIGNoYW5uZWwgMiwgd2hpY2ggd291bGQgb3RoZXJ3aXNlCj4gKwkgKiBiZSB1 bnVzZWQuCj4gKwkgKi8KPiArCWRpc3BjdHJsICY9IH5TQ0FMRVJfRElTUENUUkxfRFNQM19NVVhf TUFTSzsKPiArCWRpc3BjdHJsIHw9IFZDNF9TRVRfRklFTEQoMiwgU0NBTEVSX0RJU1BDVFJMX0RT UDNfTVVYKTsKPiArCj4gKwlIVlNfV1JJVEUoU0NBTEVSX0RJU1BDVFJMLCBkaXNwY3RybCk7Cj4g Kwo+ICAJcmV0dXJuIDA7Cj4gIH0KPiAgCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS92 YzQvdmM0X3JlZ3MuaCBiL2RyaXZlcnMvZ3B1L2RybS92YzQvdmM0X3JlZ3MuaAo+IGluZGV4IDM5 ZjY4ODZiMjQxMC4uYjNiMjk3ZmJhNzA5IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS92 YzQvdmM0X3JlZ3MuaAo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS92YzQvdmM0X3JlZ3MuaAo+IEBA IC0yNDQsNiArMjQ0LDkgQEAKPiAgIyBkZWZpbmUgU0NBTEVSX0RJU1BDVFJMX0VOQUJMRQkJCUJJ VCgzMSkKPiAgIyBkZWZpbmUgU0NBTEVSX0RJU1BDVFJMX0RTUDJFSVNMVVIJCUJJVCgxNSkKPiAg IyBkZWZpbmUgU0NBTEVSX0RJU1BDVFJMX0RTUDFFSVNMVVIJCUJJVCgxNCkKPiArIyBkZWZpbmUg U0NBTEVSX0RJU1BDVFJMX0RTUDNfTVVYX01BU0sJCVZDNF9NQVNLKDE5LCAxOCkKPiArIyBkZWZp bmUgU0NBTEVSX0RJU1BDVFJMX0RTUDNfTVVYX1NISUZUCQkxOAo+ICsKPiAgLyogRW5hYmxlcyBE aXNwbGF5IDAgc2hvcnQgbGluZSBhbmQgdW5kZXJydW4gY29udHJpYnV0aW9uIHRvCj4gICAqIFND QUxFUl9ESVNQU1RBVF9JUlFESVNQMC4gIE5vdGUgdGhhdCBzaG9ydCBmcmFtZSBjb250cmlidXRp b25zIGFyZQo+ICAgKiBhbHdheXMgZW5hYmxlZC4KPiAtLSAKPiAyLjExLjAKPiAKPiBfX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwo+IGRyaS1kZXZlbCBtYWls aW5nIGxpc3QKPiBkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCj4gaHR0cHM6Ly9saXN0 cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwKCi0tIApEYW5pZWwg VmV0dGVyClNvZnR3YXJlIEVuZ2luZWVyLCBJbnRlbCBDb3Jwb3JhdGlvbgpodHRwOi8vYmxvZy5m ZndsbC5jaApfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpk cmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0 cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK