From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752104AbdAaTj1 (ORCPT ); Tue, 31 Jan 2017 14:39:27 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:36517 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751997AbdAaTjU (ORCPT ); Tue, 31 Jan 2017 14:39:20 -0500 Date: Tue, 31 Jan 2017 20:39:01 +0100 From: Daniel Vetter To: Eric Anholt Cc: Florian Fainelli , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , dri-devel@lists.freedesktop.org, Thierry Reding , Stephen Warren , Lee Jones , linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 05/11] drm/vc4: Add support for feeding DSI encoders from the pixel valve. Message-ID: <20170131193901.dz7o5g36hqwcsmgt@phenom.ffwll.local> Mail-Followup-To: Eric Anholt , Florian Fainelli , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , dri-devel@lists.freedesktop.org, Thierry Reding , Stephen Warren , Lee Jones , linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20161214194621.16499-1-eric@anholt.net> <20161214194621.16499-6-eric@anholt.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161214194621.16499-6-eric@anholt.net> X-Operating-System: Linux phenom 4.8.0-1-amd64 User-Agent: NeoMutt/20161126 (1.7.1) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 14, 2016 at 11:46:15AM -0800, Eric Anholt wrote: > We have to set a different pixel format, which tells the hardware to > use the pix_width field that's fed in sideband from the DSI encoder to > divide the "pixel" clock. > > Signed-off-by: Eric Anholt > --- > drivers/gpu/drm/vc4/vc4_crtc.c | 33 +++++++++++++++++++-------------- > drivers/gpu/drm/vc4/vc4_regs.h | 2 ++ > 2 files changed, 21 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c > index a0fd3e66bc4b..cd070e0c79a6 100644 > --- a/drivers/gpu/drm/vc4/vc4_crtc.c > +++ b/drivers/gpu/drm/vc4/vc4_crtc.c > @@ -349,38 +349,40 @@ static u32 vc4_get_fifo_full_level(u32 format) > } > > /* > - * Returns the clock select bit for the connector attached to the > - * CRTC. > + * Returns the encoder attached to the CRTC. > + * > + * VC4 can only scan out to one encoder at a time, while the DRM core > + * allows drivers to push pixels to more than one encoder from the > + * same CRTC. > */ > -static int vc4_get_clock_select(struct drm_crtc *crtc) > +static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc) > { > struct drm_connector *connector; > > drm_for_each_connector(connector, crtc->dev) { > if (connector->state->crtc == crtc) { > - struct drm_encoder *encoder = connector->encoder; > - struct vc4_encoder *vc4_encoder = > - to_vc4_encoder(encoder); > - > - return vc4_encoder->clock_select; > + return connector->encoder; > } > } > > - return -1; > + return NULL; > } > > static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) > { > struct drm_device *dev = crtc->dev; > struct vc4_dev *vc4 = to_vc4_dev(dev); > + struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); > + struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); > struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); > struct drm_crtc_state *state = crtc->state; > struct drm_display_mode *mode = &state->adjusted_mode; > bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; > u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; > - u32 format = PV_CONTROL_FORMAT_24; > + bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || > + vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); > + u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; > bool debug_dump_regs = false; > - int clock_select = vc4_get_clock_select(crtc); > > if (debug_dump_regs) { > DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc)); > @@ -436,17 +438,19 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) > */ > CRTC_WRITE(PV_V_CONTROL, > PV_VCONTROL_CONTINUOUS | > + (is_dsi ? PV_VCONTROL_DSI : 0) | > PV_VCONTROL_INTERLACE | > VC4_SET_FIELD(mode->htotal * pixel_rep / 2, > PV_VCONTROL_ODD_DELAY)); > CRTC_WRITE(PV_VSYNCD_EVEN, 0); > } else { > - CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS); > + CRTC_WRITE(PV_V_CONTROL, > + PV_VCONTROL_CONTINUOUS | > + (is_dsi ? PV_VCONTROL_DSI : 0)); > } > > CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); > > - > CRTC_WRITE(PV_CONTROL, > VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | > VC4_SET_FIELD(vc4_get_fifo_full_level(format), > @@ -455,7 +459,8 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) > PV_CONTROL_CLR_AT_START | > PV_CONTROL_TRIGGER_UNDERFLOW | > PV_CONTROL_WAIT_HSTART | > - VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) | > + VC4_SET_FIELD(vc4_encoder->clock_select, > + PV_CONTROL_CLK_SELECT) | Hm, so the usual way we solve the "crtc needs information from the encoder problem" is to add bits to the crtc state, and then fill those out in the encoders ->atomic_check function. In your case ->clock_select and is_dsi. The benefit is mostly when you start doing hw readout (which is great even just to cross-check your modeset code), or when you need that information to check limits (which sooner or later tends to happen ime). Anyway, this works too, just an idea for the future. Acked-by: Daniel Vetter > PV_CONTROL_FIFO_CLR | > PV_CONTROL_EN); > > diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h > index b3b297fba709..385405a2df05 100644 > --- a/drivers/gpu/drm/vc4/vc4_regs.h > +++ b/drivers/gpu/drm/vc4/vc4_regs.h > @@ -190,6 +190,8 @@ > # define PV_VCONTROL_ODD_DELAY_SHIFT 6 > # define PV_VCONTROL_ODD_FIRST BIT(5) > # define PV_VCONTROL_INTERLACE BIT(4) > +# define PV_VCONTROL_DSI BIT(3) > +# define PV_VCONTROL_COMMAND BIT(2) > # define PV_VCONTROL_CONTINUOUS BIT(1) > # define PV_VCONTROL_VIDEN BIT(0) > > -- > 2.11.0 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From mboxrd@z Thu Jan 1 00:00:00 1970 From: daniel@ffwll.ch (Daniel Vetter) Date: Tue, 31 Jan 2017 20:39:01 +0100 Subject: [PATCH 05/11] drm/vc4: Add support for feeding DSI encoders from the pixel valve. In-Reply-To: <20161214194621.16499-6-eric@anholt.net> References: <20161214194621.16499-1-eric@anholt.net> <20161214194621.16499-6-eric@anholt.net> Message-ID: <20170131193901.dz7o5g36hqwcsmgt@phenom.ffwll.local> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Dec 14, 2016 at 11:46:15AM -0800, Eric Anholt wrote: > We have to set a different pixel format, which tells the hardware to > use the pix_width field that's fed in sideband from the DSI encoder to > divide the "pixel" clock. > > Signed-off-by: Eric Anholt > --- > drivers/gpu/drm/vc4/vc4_crtc.c | 33 +++++++++++++++++++-------------- > drivers/gpu/drm/vc4/vc4_regs.h | 2 ++ > 2 files changed, 21 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c > index a0fd3e66bc4b..cd070e0c79a6 100644 > --- a/drivers/gpu/drm/vc4/vc4_crtc.c > +++ b/drivers/gpu/drm/vc4/vc4_crtc.c > @@ -349,38 +349,40 @@ static u32 vc4_get_fifo_full_level(u32 format) > } > > /* > - * Returns the clock select bit for the connector attached to the > - * CRTC. > + * Returns the encoder attached to the CRTC. > + * > + * VC4 can only scan out to one encoder at a time, while the DRM core > + * allows drivers to push pixels to more than one encoder from the > + * same CRTC. > */ > -static int vc4_get_clock_select(struct drm_crtc *crtc) > +static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc) > { > struct drm_connector *connector; > > drm_for_each_connector(connector, crtc->dev) { > if (connector->state->crtc == crtc) { > - struct drm_encoder *encoder = connector->encoder; > - struct vc4_encoder *vc4_encoder = > - to_vc4_encoder(encoder); > - > - return vc4_encoder->clock_select; > + return connector->encoder; > } > } > > - return -1; > + return NULL; > } > > static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) > { > struct drm_device *dev = crtc->dev; > struct vc4_dev *vc4 = to_vc4_dev(dev); > + struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); > + struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); > struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); > struct drm_crtc_state *state = crtc->state; > struct drm_display_mode *mode = &state->adjusted_mode; > bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; > u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; > - u32 format = PV_CONTROL_FORMAT_24; > + bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || > + vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); > + u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; > bool debug_dump_regs = false; > - int clock_select = vc4_get_clock_select(crtc); > > if (debug_dump_regs) { > DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc)); > @@ -436,17 +438,19 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) > */ > CRTC_WRITE(PV_V_CONTROL, > PV_VCONTROL_CONTINUOUS | > + (is_dsi ? PV_VCONTROL_DSI : 0) | > PV_VCONTROL_INTERLACE | > VC4_SET_FIELD(mode->htotal * pixel_rep / 2, > PV_VCONTROL_ODD_DELAY)); > CRTC_WRITE(PV_VSYNCD_EVEN, 0); > } else { > - CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS); > + CRTC_WRITE(PV_V_CONTROL, > + PV_VCONTROL_CONTINUOUS | > + (is_dsi ? PV_VCONTROL_DSI : 0)); > } > > CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); > > - > CRTC_WRITE(PV_CONTROL, > VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | > VC4_SET_FIELD(vc4_get_fifo_full_level(format), > @@ -455,7 +459,8 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) > PV_CONTROL_CLR_AT_START | > PV_CONTROL_TRIGGER_UNDERFLOW | > PV_CONTROL_WAIT_HSTART | > - VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) | > + VC4_SET_FIELD(vc4_encoder->clock_select, > + PV_CONTROL_CLK_SELECT) | Hm, so the usual way we solve the "crtc needs information from the encoder problem" is to add bits to the crtc state, and then fill those out in the encoders ->atomic_check function. In your case ->clock_select and is_dsi. The benefit is mostly when you start doing hw readout (which is great even just to cross-check your modeset code), or when you need that information to check limits (which sooner or later tends to happen ime). Anyway, this works too, just an idea for the future. Acked-by: Daniel Vetter > PV_CONTROL_FIFO_CLR | > PV_CONTROL_EN); > > diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h > index b3b297fba709..385405a2df05 100644 > --- a/drivers/gpu/drm/vc4/vc4_regs.h > +++ b/drivers/gpu/drm/vc4/vc4_regs.h > @@ -190,6 +190,8 @@ > # define PV_VCONTROL_ODD_DELAY_SHIFT 6 > # define PV_VCONTROL_ODD_FIRST BIT(5) > # define PV_VCONTROL_INTERLACE BIT(4) > +# define PV_VCONTROL_DSI BIT(3) > +# define PV_VCONTROL_COMMAND BIT(2) > # define PV_VCONTROL_CONTINUOUS BIT(1) > # define PV_VCONTROL_VIDEN BIT(0) > > -- > 2.11.0 > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 05/11] drm/vc4: Add support for feeding DSI encoders from the pixel valve. Date: Tue, 31 Jan 2017 20:39:01 +0100 Message-ID: <20170131193901.dz7o5g36hqwcsmgt@phenom.ffwll.local> References: <20161214194621.16499-1-eric@anholt.net> <20161214194621.16499-6-eric@anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id 74C996E2A5 for ; Tue, 31 Jan 2017 19:39:06 +0000 (UTC) Received: by mail-wm0-x241.google.com with SMTP id r18so439825wmd.3 for ; Tue, 31 Jan 2017 11:39:06 -0800 (PST) Content-Disposition: inline In-Reply-To: <20161214194621.16499-6-eric@anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Eric Anholt Cc: Mark Rutland , Florian Fainelli , Stephen Warren , Michael Turquette , Lee Jones , Stephen Boyd , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: dri-devel@lists.freedesktop.org T24gV2VkLCBEZWMgMTQsIDIwMTYgYXQgMTE6NDY6MTVBTSAtMDgwMCwgRXJpYyBBbmhvbHQgd3Jv dGU6Cj4gV2UgaGF2ZSB0byBzZXQgYSBkaWZmZXJlbnQgcGl4ZWwgZm9ybWF0LCB3aGljaCB0ZWxs cyB0aGUgaGFyZHdhcmUgdG8KPiB1c2UgdGhlIHBpeF93aWR0aCBmaWVsZCB0aGF0J3MgZmVkIGlu IHNpZGViYW5kIGZyb20gdGhlIERTSSBlbmNvZGVyIHRvCj4gZGl2aWRlIHRoZSAicGl4ZWwiIGNs b2NrLgo+IAo+IFNpZ25lZC1vZmYtYnk6IEVyaWMgQW5ob2x0IDxlcmljQGFuaG9sdC5uZXQ+Cj4g LS0tCj4gIGRyaXZlcnMvZ3B1L2RybS92YzQvdmM0X2NydGMuYyB8IDMzICsrKysrKysrKysrKysr KysrKystLS0tLS0tLS0tLS0tLQo+ICBkcml2ZXJzL2dwdS9kcm0vdmM0L3ZjNF9yZWdzLmggfCAg MiArKwo+ICAyIGZpbGVzIGNoYW5nZWQsIDIxIGluc2VydGlvbnMoKyksIDE0IGRlbGV0aW9ucygt KQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vdmM0L3ZjNF9jcnRjLmMgYi9kcml2 ZXJzL2dwdS9kcm0vdmM0L3ZjNF9jcnRjLmMKPiBpbmRleCBhMGZkM2U2NmJjNGIuLmNkMDcwZTBj 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