diff for duplicates of <20170207183042.62699-9-icenowy@aosc.xyz>
diff --git a/a/1.txt b/N1/1.txt
index 13523fd..c6c95ab 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,4 +1,4 @@
-From: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
+From: Andre Przywara <andre.przywara@arm.com>
The Allwinner H5 SoC is pin-compatible to the H3 SoC, but uses
Cortex-A53 cores instead.
@@ -6,12 +6,12 @@ Based on the now shared base .dtsi describing the common peripherals
describe the H5 specific nodes on top of that.
That symlinks in the sunxi-h3-h5.dtsi from the arch/arm tree.
-Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Icenowy: add H5 pinctrl compatible, and changes for my h3-h5 dtsi
refactor, commit message change to met new arm64 naming scheme,
drop H3 pinctrl compatible because of interrupt bank change, drop
H3 ccu compatible because of clock change]
-Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
+Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes in v3:
- Dropped sun5i-a13-mmc, sun8i-h3-ccu compatibles.
@@ -82,28 +82,28 @@ index 000000000000..b651bd6986e8
+ #address-cells = <1>;
+ #size-cells = <0>;
+
-+ cpu@0 {
++ cpu at 0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+
-+ cpu@1 {
++ cpu at 1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+
-+ cpu@2 {
++ cpu at 2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ };
+
-+ cpu@3 {
++ cpu at 3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <3>;
@@ -129,7 +129,7 @@ index 000000000000..b651bd6986e8
+ };
+
+ soc {
-+ gic: interrupt-controller@1c81000 {
++ gic: interrupt-controller at 1c81000 {
+ compatible = "arm,gic-400";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x2000>,
diff --git a/a/content_digest b/N1/content_digest
index 2b11113..5cbb450 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,10 +2,7 @@
"ref\00020170207183042.62699-1-icenowy\@aosc.xyz\0"
]
[
- "ref\00020170207183042.62699-1-icenowy-ymACFijhrKM\@public.gmane.org\0"
-]
-[
- "From\0Icenowy Zheng <icenowy-ymACFijhrKM\@public.gmane.org>\0"
+ "From\0icenowy\@aosc.xyz (Icenowy Zheng)\0"
]
[
"Subject\0[PATCH v4 8/9] arm64: dts: allwinner: add Allwinner H5 .dtsi\0"
@@ -14,23 +11,7 @@
"Date\0Wed, 8 Feb 2017 02:30:41 +0800\0"
]
[
- "To\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8\@public.gmane.org>",
- " Chen-Yu Tsai <wens-jdAy2FN1RRM\@public.gmane.org>",
- " Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw\@public.gmane.org>",
- " Catalin Marinas <catalin.marinas-5wv7dgnIgG8\@public.gmane.org>",
- " Will Deacon <will.deacon-5wv7dgnIgG8\@public.gmane.org>",
- " Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A\@public.gmane.org>",
- " Jaroslav Kysela <perex-/Fr2/VpizcU\@public.gmane.org>",
- " Andre Przywara <andre.przywara-5wv7dgnIgG8\@public.gmane.org>\0"
-]
-[
- "Cc\0linux-clk-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " devicetree-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r\@public.gmane.org",
- " linux-kernel-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw\@public.gmane.org",
- " linux-sunxi-/JYPxA39Uh5TLH3MbocFFw\@public.gmane.org",
- " Icenowy Zheng <icenowy-ymACFijhrKM\@public.gmane.org>\0"
+ "To\0linux-arm-kernel\@lists.infradead.org\0"
]
[
"\0000:1\0"
@@ -39,7 +20,7 @@
"b\0"
]
[
- "From: Andre Przywara <andre.przywara-5wv7dgnIgG8\@public.gmane.org>\n",
+ "From: Andre Przywara <andre.przywara\@arm.com>\n",
"\n",
"The Allwinner H5 SoC is pin-compatible to the H3 SoC, but uses\n",
"Cortex-A53 cores instead.\n",
@@ -47,12 +28,12 @@
"describe the H5 specific nodes on top of that.\n",
"That symlinks in the sunxi-h3-h5.dtsi from the arch/arm tree.\n",
"\n",
- "Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8\@public.gmane.org>\n",
+ "Signed-off-by: Andre Przywara <andre.przywara\@arm.com>\n",
"[Icenowy: add H5 pinctrl compatible, and changes for my h3-h5 dtsi\n",
" refactor, commit message change to met new arm64 naming scheme,\n",
" drop H3 pinctrl compatible because of interrupt bank change, drop\n",
" H3 ccu compatible because of clock change]\n",
- "Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM\@public.gmane.org>\n",
+ "Signed-off-by: Icenowy Zheng <icenowy\@aosc.xyz>\n",
"---\n",
"Changes in v3:\n",
"- Dropped sun5i-a13-mmc, sun8i-h3-ccu compatibles.\n",
@@ -123,28 +104,28 @@
"+\t\t#address-cells = <1>;\n",
"+\t\t#size-cells = <0>;\n",
"+\n",
- "+\t\tcpu\@0 {\n",
+ "+\t\tcpu at 0 {\n",
"+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\treg = <0>;\n",
"+\t\t\tenable-method = \"psci\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu\@1 {\n",
+ "+\t\tcpu at 1 {\n",
"+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\treg = <1>;\n",
"+\t\t\tenable-method = \"psci\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu\@2 {\n",
+ "+\t\tcpu at 2 {\n",
"+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\treg = <2>;\n",
"+\t\t\tenable-method = \"psci\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu\@3 {\n",
+ "+\t\tcpu at 3 {\n",
"+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\treg = <3>;\n",
@@ -170,7 +151,7 @@
"+\t};\n",
"+\n",
"+\tsoc {\n",
- "+\t\tgic: interrupt-controller\@1c81000 {\n",
+ "+\t\tgic: interrupt-controller at 1c81000 {\n",
"+\t\t\tcompatible = \"arm,gic-400\";\n",
"+\t\t\treg = <0x01c81000 0x1000>,\n",
"+\t\t\t <0x01c82000 0x2000>,\n",
@@ -223,4 +204,4 @@
"2.11.0"
]
-38b51ab2d0ee7f1fac561bfd7584613ff3e074fb0e52af2cc888cf17f8c91866
+d9040e2e01b294849e4bd0e17810d46eeab81ddb8650c2b0a8a0d64e3a706b47
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.