From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH 6/8] arm64: dts: allwinner: add device node for R_PWM Date: Wed, 8 Feb 2017 11:17:06 +0100 Message-ID: <20170208101706.332djd3fw6tbenqx@lukather> References: <20170208100009.29362-1-icenowy@aosc.xyz> <20170208100009.29362-6-icenowy@aosc.xyz> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="j7fex3yqge4ngjh5" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20170208100009.29362-6-icenowy-ymACFijhrKM@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Icenowy Zheng Cc: Linus Walleij , Rob Herring , Chen-Yu Tsai , Catalin Marinas , Will Deacon , linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: linux-gpio@vger.kernel.org --j7fex3yqge4ngjh5 Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Wed, Feb 08, 2017 at 06:00:07PM +0800, Icenowy Zheng wrote: > Allwinner A64 SoC has two PWM controller, both are similar to the > controller in H3 SoC. > > Add one of the controllers which lies in the "CPUs" part of the SoC. > > Signed-off-by: Icenowy Zheng > --- > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > index 4b0baa79554c..6204aee5c6f4 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > @@ -432,5 +432,13 @@ > #size-cells = <0>; > #gpio-cells = <3>; > }; > + > + r_pwm: pwm@01f03800 { > + compatible = "allwinner,sun8i-h3-pwm"; Please add an a64 compatible there too. > + reg = <0x01f03800 0x8>; The size is 0x400 Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --j7fex3yqge4ngjh5-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753593AbdBHKlG (ORCPT ); Wed, 8 Feb 2017 05:41:06 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:41108 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752160AbdBHKlE (ORCPT ); Wed, 8 Feb 2017 05:41:04 -0500 Date: Wed, 8 Feb 2017 11:17:06 +0100 From: Maxime Ripard To: Icenowy Zheng Cc: Linus Walleij , Rob Herring , Chen-Yu Tsai , Catalin Marinas , Will Deacon , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH 6/8] arm64: dts: allwinner: add device node for R_PWM Message-ID: <20170208101706.332djd3fw6tbenqx@lukather> References: <20170208100009.29362-1-icenowy@aosc.xyz> <20170208100009.29362-6-icenowy@aosc.xyz> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="j7fex3yqge4ngjh5" Content-Disposition: inline In-Reply-To: <20170208100009.29362-6-icenowy@aosc.xyz> User-Agent: Mutt/1.6.2-neo (2016-08-21) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --j7fex3yqge4ngjh5 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Feb 08, 2017 at 06:00:07PM +0800, Icenowy Zheng wrote: > Allwinner A64 SoC has two PWM controller, both are similar to the > controller in H3 SoC. >=20 > Add one of the controllers which lies in the "CPUs" part of the SoC. >=20 > Signed-off-by: Icenowy Zheng > --- > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/b= oot/dts/allwinner/sun50i-a64.dtsi > index 4b0baa79554c..6204aee5c6f4 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > @@ -432,5 +432,13 @@ > #size-cells =3D <0>; > #gpio-cells =3D <3>; > }; > + > + r_pwm: pwm@01f03800 { > + compatible =3D "allwinner,sun8i-h3-pwm"; Please add an a64 compatible there too. > + reg =3D <0x01f03800 0x8>; The size is 0x400 Thanks, Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --j7fex3yqge4ngjh5 Content-Type: application/pgp-signature; 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> #gpio-cells = <3>; > }; > + > + r_pwm: pwm at 01f03800 { > + compatible = "allwinner,sun8i-h3-pwm"; Please add an a64 compatible there too. > + reg = <0x01f03800 0x8>; The size is 0x400 Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... 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