From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: Re: ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Use a heavyweight irq-seqno barrier for gen6+
Date: Wed, 15 Feb 2017 16:09:05 +0000 [thread overview]
Message-ID: <20170215160905.GG18048@nuc-i3427.alporthouse.com> (raw)
In-Reply-To: <20170215160333.GF18048@nuc-i3427.alporthouse.com>
On Wed, Feb 15, 2017 at 04:03:33PM +0000, Chris Wilson wrote:
> On Wed, Feb 15, 2017 at 01:52:12PM -0000, Patchwork wrote:
> > == Series Details ==
> >
> > Series: series starting with [1/2] drm/i915: Use a heavyweight irq-seqno barrier for gen6+
> > URL : https://patchwork.freedesktop.org/series/19697/
> > State : failure
> >
> > == Summary ==
> >
> > Series 19697v1 Series without cover letter
> > https://patchwork.freedesktop.org/api/1.0/series/19697/revisions/1/mbox/
> >
> > Test gem_sync:
> > Subgroup basic-store-each:
> > pass -> FAIL (fi-ilk-650)
>
> But that rules out this method as being the "ideal" delay. Back to the
> drawing board.
And the failure on hang tells me that the SyncFlush only occurs between
CS steps (and not inside batches). As demonstrated aptly by the hanging
batch, that is itself less than ideal.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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prev parent reply other threads:[~2017-02-15 16:09 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-15 11:36 [PATCH 1/2] drm/i915: Use a heavyweight irq-seqno barrier for gen6+ Chris Wilson
2017-02-15 11:36 ` [PATCH 2/2] drm/i915: Share the heavyweight sync-flush irq barrier with gen5 Chris Wilson
2017-02-15 11:59 ` [PATCH 1/2] drm/i915: Use a heavyweight irq-seqno barrier for gen6+ Ville Syrjälä
2017-02-15 12:15 ` Chris Wilson
2017-02-15 12:32 ` Ville Syrjälä
2017-02-15 16:00 ` Chris Wilson
2017-02-15 13:52 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] " Patchwork
2017-02-15 16:03 ` Chris Wilson
2017-02-15 16:09 ` Chris Wilson [this message]
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