From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751773AbdBOUJF (ORCPT ); Wed, 15 Feb 2017 15:09:05 -0500 Received: from mail-it0-f42.google.com ([209.85.214.42]:33501 "EHLO mail-it0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751430AbdBOUJC (ORCPT ); Wed, 15 Feb 2017 15:09:02 -0500 Date: Wed, 15 Feb 2017 13:08:58 -0700 From: Mathieu Poirier To: Leo Yan Cc: Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Thompson Subject: Re: [PATCH RFC 1/3] coresight: binding for coresight debug driver Message-ID: <20170215200858.GA29730@linaro.org> References: <1486966298-16767-1-git-send-email-leo.yan@linaro.org> <1486966298-16767-2-git-send-email-leo.yan@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1486966298-16767-2-git-send-email-leo.yan@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Feb 13, 2017 at 02:11:36PM +0800, Leo Yan wrote: > Adding compatible string for new coresight debug driver. > Hi Leo, I agree with Mark, this will need a better description. > Signed-off-by: Leo Yan > --- > Documentation/devicetree/bindings/arm/coresight.txt | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt > index fcbae6a..3ff15fd 100644 > --- a/Documentation/devicetree/bindings/arm/coresight.txt > +++ b/Documentation/devicetree/bindings/arm/coresight.txt > @@ -40,6 +40,9 @@ its hardware characteristcs. > - System Trace Macrocell: > "arm,coresight-stm", "arm,primecell"; [1] > > + - Debug Unit: > + "arm,coresight-debug", "arm,primecell"; > + Humm... The current CoreSight bindings are meant to describe IPs included in the HW assisted trace architecture. This new driver, althought considered to be part of the CoreSight umbrella, falls under the debugging domain. Adding the bindings in this file may lead people to beleive this driver fits into the CoreSight framework currently supported, which isn't the case. As such it is probably a good idea to spin off a new file, "coresight-debug.txt" to handle this driver. Mark, what's your take on this? > * reg: physical base address and length of the register > set(s) of the component. > > @@ -78,8 +81,10 @@ its hardware characteristcs. > * arm,cp14: must be present if the system accesses ETM/PTM management > registers via co-processor 14. > > - * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the > - source is considered to belong to CPU0. > +* Optional properties for ETM/PTM/Debugs: > + > + * cpu: the cpu phandle this ETM/PTM/Debug is affined to. When omitted > + the source is considered to belong to CPU0. > > * Optional property for TMC: > > -- > 2.7.4 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mathieu Poirier Subject: Re: [PATCH RFC 1/3] coresight: binding for coresight debug driver Date: Wed, 15 Feb 2017 13:08:58 -0700 Message-ID: <20170215200858.GA29730@linaro.org> References: <1486966298-16767-1-git-send-email-leo.yan@linaro.org> <1486966298-16767-2-git-send-email-leo.yan@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1486966298-16767-2-git-send-email-leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Leo Yan Cc: Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Daniel Thompson List-Id: devicetree@vger.kernel.org On Mon, Feb 13, 2017 at 02:11:36PM +0800, Leo Yan wrote: > Adding compatible string for new coresight debug driver. > Hi Leo, I agree with Mark, this will need a better description. > Signed-off-by: Leo Yan > --- > Documentation/devicetree/bindings/arm/coresight.txt | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt > index fcbae6a..3ff15fd 100644 > --- a/Documentation/devicetree/bindings/arm/coresight.txt > +++ b/Documentation/devicetree/bindings/arm/coresight.txt > @@ -40,6 +40,9 @@ its hardware characteristcs. > - System Trace Macrocell: > "arm,coresight-stm", "arm,primecell"; [1] > > + - Debug Unit: > + "arm,coresight-debug", "arm,primecell"; > + Humm... The current CoreSight bindings are meant to describe IPs included in the HW assisted trace architecture. This new driver, althought considered to be part of the CoreSight umbrella, falls under the debugging domain. Adding the bindings in this file may lead people to beleive this driver fits into the CoreSight framework currently supported, which isn't the case. As such it is probably a good idea to spin off a new file, "coresight-debug.txt" to handle this driver. Mark, what's your take on this? > * reg: physical base address and length of the register > set(s) of the component. > > @@ -78,8 +81,10 @@ its hardware characteristcs. > * arm,cp14: must be present if the system accesses ETM/PTM management > registers via co-processor 14. > > - * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the > - source is considered to belong to CPU0. > +* Optional properties for ETM/PTM/Debugs: > + > + * cpu: the cpu phandle this ETM/PTM/Debug is affined to. When omitted > + the source is considered to belong to CPU0. > > * Optional property for TMC: > > -- > 2.7.4 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: mathieu.poirier@linaro.org (Mathieu Poirier) Date: Wed, 15 Feb 2017 13:08:58 -0700 Subject: [PATCH RFC 1/3] coresight: binding for coresight debug driver In-Reply-To: <1486966298-16767-2-git-send-email-leo.yan@linaro.org> References: <1486966298-16767-1-git-send-email-leo.yan@linaro.org> <1486966298-16767-2-git-send-email-leo.yan@linaro.org> Message-ID: <20170215200858.GA29730@linaro.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Feb 13, 2017 at 02:11:36PM +0800, Leo Yan wrote: > Adding compatible string for new coresight debug driver. > Hi Leo, I agree with Mark, this will need a better description. > Signed-off-by: Leo Yan > --- > Documentation/devicetree/bindings/arm/coresight.txt | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt > index fcbae6a..3ff15fd 100644 > --- a/Documentation/devicetree/bindings/arm/coresight.txt > +++ b/Documentation/devicetree/bindings/arm/coresight.txt > @@ -40,6 +40,9 @@ its hardware characteristcs. > - System Trace Macrocell: > "arm,coresight-stm", "arm,primecell"; [1] > > + - Debug Unit: > + "arm,coresight-debug", "arm,primecell"; > + Humm... The current CoreSight bindings are meant to describe IPs included in the HW assisted trace architecture. This new driver, althought considered to be part of the CoreSight umbrella, falls under the debugging domain. Adding the bindings in this file may lead people to beleive this driver fits into the CoreSight framework currently supported, which isn't the case. As such it is probably a good idea to spin off a new file, "coresight-debug.txt" to handle this driver. Mark, what's your take on this? > * reg: physical base address and length of the register > set(s) of the component. > > @@ -78,8 +81,10 @@ its hardware characteristcs. > * arm,cp14: must be present if the system accesses ETM/PTM management > registers via co-processor 14. > > - * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the > - source is considered to belong to CPU0. > +* Optional properties for ETM/PTM/Debugs: > + > + * cpu: the cpu phandle this ETM/PTM/Debug is affined to. When omitted > + the source is considered to belong to CPU0. > > * Optional property for TMC: > > -- > 2.7.4 >