From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Brandt Subject: [PATCH v3 3/3] ARM: dts: r7s72100: add l2 cache Date: Thu, 16 Feb 2017 10:37:26 -0500 Message-ID: <20170216153726.22919-4-chris.brandt@renesas.com> References: <20170216153726.22919-1-chris.brandt@renesas.com> Return-path: In-Reply-To: <20170216153726.22919-1-chris.brandt@renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org To: Simon Horman , Magnus Damm , Geert Uytterhoeven , Rob Herring , Mark Rutland , Russell King , Brad Mouring , Andrey Smirnov , Arnd Bergmann , Richard Cochran Cc: devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Brandt List-Id: devicetree@vger.kernel.org Note that early-bresp-disable and full-line-zero-disable are required because the sideband signals between the CPU and L2C were not connected in this SoC. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- v3: * split "arm,pl310-no-sideband" into "arm,early-bresp-disable" and "arm,full-line-zero-disable" v2: * added "arm,pl310-no-sideband" --- arch/arm/boot/dts/r7s72100.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 614ba79..ed62e19 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -180,6 +180,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <400000000>; + next-level-cache = <&L2>; }; }; @@ -371,6 +372,16 @@ <0xe8202000 0x1000>; }; + L2: cache-controller@3ffff000 { + compatible = "arm,pl310-cache"; + reg = <0x3ffff000 0x1000>; + interrupts = ; + arm,early-bresp-disable; + arm,full-line-zero-disable; + cache-unified; + cache-level = <2>; + }; + i2c0: i2c@fcfee000 { #address-cells = <1>; #size-cells = <0>; -- 2.10.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: chris.brandt@renesas.com (Chris Brandt) Date: Thu, 16 Feb 2017 10:37:26 -0500 Subject: [PATCH v3 3/3] ARM: dts: r7s72100: add l2 cache In-Reply-To: <20170216153726.22919-1-chris.brandt@renesas.com> References: <20170216153726.22919-1-chris.brandt@renesas.com> Message-ID: <20170216153726.22919-4-chris.brandt@renesas.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Note that early-bresp-disable and full-line-zero-disable are required because the sideband signals between the CPU and L2C were not connected in this SoC. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- v3: * split "arm,pl310-no-sideband" into "arm,early-bresp-disable" and "arm,full-line-zero-disable" v2: * added "arm,pl310-no-sideband" --- arch/arm/boot/dts/r7s72100.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 614ba79..ed62e19 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -180,6 +180,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <400000000>; + next-level-cache = <&L2>; }; }; @@ -371,6 +372,16 @@ <0xe8202000 0x1000>; }; + L2: cache-controller at 3ffff000 { + compatible = "arm,pl310-cache"; + reg = <0x3ffff000 0x1000>; + interrupts = ; + arm,early-bresp-disable; + arm,full-line-zero-disable; + cache-unified; + cache-level = <2>; + }; + i2c0: i2c at fcfee000 { #address-cells = <1>; #size-cells = <0>; -- 2.10.1