From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com ([134.134.136.20]:63997 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932218AbdBPRqa (ORCPT ); Thu, 16 Feb 2017 12:46:30 -0500 Date: Thu, 16 Feb 2017 19:46:26 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Manasi Navare Cc: intel-gfx@lists.freedesktop.org, Palmer Dabbelt , stable@vger.kernel.org Subject: Re: [Intel-gfx] [PATCH] drm/i915: Perform link quality check unconditionally during long pulse Message-ID: <20170216174626.GJ31595@intel.com> References: <20170216152659.GD31595@intel.com> <20170216153007.14868-1-ville.syrjala@linux.intel.com> <20170216170753.GA27437@intel.com> <20170216171857.GI31595@intel.com> <20170216172409.GB27437@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20170216172409.GB27437@intel.com> Sender: stable-owner@vger.kernel.org List-ID: On Thu, Feb 16, 2017 at 09:24:09AM -0800, Manasi Navare wrote: > On Thu, Feb 16, 2017 at 07:18:57PM +0200, Ville Syrj�l� wrote: > > On Thu, Feb 16, 2017 at 09:07:53AM -0800, Manasi Navare wrote: > > > On Thu, Feb 16, 2017 at 05:30:07PM +0200, ville.syrjala@linux.intel.com wrote: > > > > From: Ville Syrj�l� > > > > > > > > Apparently some DP sinks are a little nuts and cause HPD to drop > > > > intermittently during modesets. This happens eg. on an ASUS PB287Q. > > > > In oder to recover from this we can't really use the previous > > > > connector status to determine if the link needs retraining, so let's > > > > just ignore that piece of information and do the retrain > > > > unconditionally. We do of course still check whether the link is > > > > supposed to be running or not. > > > > > > > > Cc: stable@vger.kernel.org > > > > Cc: Palmer Dabbelt > > > > Reported-by: Palmer Dabbelt > > > > References: https://lists.freedesktop.org/archives/intel-gfx/2017-February/119779.html > > > > Signed-off-by: Ville Syrj�l� > > > > --- > > > > drivers/gpu/drm/i915/intel_dp.c | 15 +++++++++++---- > > > > 1 file changed, 11 insertions(+), 4 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > > > index 024798a9c016..37a746f7fbc3 100644 > > > > --- a/drivers/gpu/drm/i915/intel_dp.c > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > > > @@ -4648,11 +4648,18 @@ intel_dp_long_pulse(struct intel_connector *intel_connector) > > > > */ > > > > status = connector_status_disconnected; > > > > goto out; > > > > - } else if (connector->status == connector_status_connected) { > > > > + } else { > > > > /* > > > > - * If display was connected already and is still connected > > > > - * check links status, there has been known issues of > > > > - * link loss triggerring long pulse!!!! > > > > + * If display is now connected check links status, > > > > + * there has been known issues of link loss triggerring > > > > + * long pulse. > > > > + * > > > > + * Some sinks (eg. ASUS PB287Q) seem to perform some > > > > + * weird HPD ping pong during modesets. So we can apparely > > > > + * end up with HPD going low during a modeset, and then > > > > + * going back up soon after. And once that happens we must > > > > + * retrain the link to get a picture. That's in case no > > > > + * userspace component reacted to intermittent HPD dip. > > > > */ > > > > drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); > > > > intel_dp_check_link_status(intel_dp); > > > > -- > > > > > > So here we basically just ignore the connector status and retrain irrespectively. > > > > We ignore the _previous_ connector status. > > > > > But that means even if we have newer values now for max link rate/lane count from > > > DPCD, during this retrain we are just using the stale value of intel_dp->link_rate > > > and intel_dp->lane_count. I think intel_dp->link_rate and lane count values > > > should be set to 0 on HPD pulse, they would be set only during a modeset. > > > > The DPCD has already been parsed by this time. > > > > -- > > Ville Syrj�l� > > Intel OTC > > Yes, we have parsed the DPCD but we dont write to intel_dp->link-rate and intel_dp->lane_count > until we do a modeset (these get written during pre_enable) and these values get used > during the retraining of the link. So at this point we will still use stale values. They're not stale. They're exactly what we used when we set up the mode that's still being drive out. This is just retraining the link at the same parameters. > Shouldnt we set the link status to BAD and send a hotplug event, like the solution we implemneted > for retraining? > > Regards > Manasi > > Regards > Manasi -- Ville Syrj�l� Intel OTC From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Perform link quality check unconditionally during long pulse Date: Thu, 16 Feb 2017 19:46:26 +0200 Message-ID: <20170216174626.GJ31595@intel.com> References: <20170216152659.GD31595@intel.com> <20170216153007.14868-1-ville.syrjala@linux.intel.com> <20170216170753.GA27437@intel.com> <20170216171857.GI31595@intel.com> <20170216172409.GB27437@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id CCCC36EBF0 for ; Thu, 16 Feb 2017 17:46:29 +0000 (UTC) Content-Disposition: inline In-Reply-To: <20170216172409.GB27437@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Manasi Navare Cc: intel-gfx@lists.freedesktop.org, Palmer Dabbelt , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org T24gVGh1LCBGZWIgMTYsIDIwMTcgYXQgMDk6MjQ6MDlBTSAtMDgwMCwgTWFuYXNpIE5hdmFyZSB3 cm90ZToKPiBPbiBUaHUsIEZlYiAxNiwgMjAxNyBhdCAwNzoxODo1N1BNICswMjAwLCBWaWxsZSBT eXJqw6Rsw6Qgd3JvdGU6Cj4gPiBPbiBUaHUsIEZlYiAxNiwgMjAxNyBhdCAwOTowNzo1M0FNIC0w ODAwLCBNYW5hc2kgTmF2YXJlIHdyb3RlOgo+ID4gPiBPbiBUaHUsIEZlYiAxNiwgMjAxNyBhdCAw NTozMDowN1BNICswMjAwLCB2aWxsZS5zeXJqYWxhQGxpbnV4LmludGVsLmNvbSB3cm90ZToKPiA+ ID4gPiBGcm9tOiBWaWxsZSBTeXJqw6Rsw6QgPHZpbGxlLnN5cmphbGFAbGludXguaW50ZWwuY29t Pgo+ID4gPiA+IAo+ID4gPiA+IEFwcGFyZW50bHkgc29tZSBEUCBzaW5rcyBhcmUgYSBsaXR0bGUg bnV0cyBhbmQgY2F1c2UgSFBEIHRvIGRyb3AKPiA+ID4gPiBpbnRlcm1pdHRlbnRseSBkdXJpbmcg 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