From mboxrd@z Thu Jan  1 00:00:00 1970
From: Haozhong Zhang <haozhong.zhang@intel.com>
Subject: [PATCH 10/19] x86/mce: always write 0 to
	MSR_IA32_MCG_STATUS on Intel CPU
Date: Fri, 17 Feb 2017 14:39:27 +0800
Message-ID: <20170217063936.13208-11-haozhong.zhang@intel.com>
References: <20170217063936.13208-1-haozhong.zhang@intel.com>
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Cc: Haozhong Zhang <haozhong.zhang@intel.com>, Christoph Egger <chegger@amazon.de>, Andrew Cooper <andrew.cooper3@citrix.com>, Jan Beulich <jbeulich@suse.com>, Liu Jinsong <jinsong.liu@alibaba-inc.com>
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QW4gYXR0ZW1wIHRvIHdyaXRlIHRvIE1TUl9JQTMyX01DR19TVEFUVVMgd2l0aCBhbnkgdmFsdWUg
b3RoZXIgdGhhbiAwCndvdWxkIHJlc3VsdCBpbiAjR1Agb24gSW50ZWwgQ1BVLgoKU2lnbmVkLW9m
Zi1ieTogSGFvemhvbmcgWmhhbmcgPGhhb3pob25nLnpoYW5nQGludGVsLmNvbT4KLS0tCkNjOiBD
aHJpc3RvcGggRWdnZXIgPGNoZWdnZXJAYW1hem9uLmRlPgpDYzogTGl1IEppbnNvbmcgPGppbnNv
bmcubGl1QGFsaWJhYmEtaW5jLmNvbT4KQ2M6IEphbiBCZXVsaWNoIDxqYmV1bGljaEBzdXNlLmNv
bT4KQ2M6IEFuZHJldyBDb29wZXIgPGFuZHJldy5jb29wZXIzQGNpdHJpeC5jb20+Ci0tLQogeGVu
L2FyY2gveDg2L2NwdS9tY2hlY2svbWNlLmMgfCA5ICsrKysrKysrLQogMSBmaWxlIGNoYW5nZWQs
IDggaW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbigtKQoKZGlmZiAtLWdpdCBhL3hlbi9hcmNoL3g4
Ni9jcHUvbWNoZWNrL21jZS5jIGIveGVuL2FyY2gveDg2L2NwdS9tY2hlY2svbWNlLmMKaW5kZXgg
MjhiZjU3OS4uOTVhOWRhMyAxMDA2NDQKLS0tIGEveGVuL2FyY2gveDg2L2NwdS9tY2hlY2svbWNl
LmMKKysrIGIveGVuL2FyY2gveDg2L2NwdS9tY2hlY2svbWNlLmMKQEAgLTUzOCw3ICs1MzgsMTQg
QEAgdm9pZCBtY2hlY2tfY21uX2hhbmRsZXIoY29uc3Qgc3RydWN0IGNwdV91c2VyX3JlZ3MgKnJl
Z3MpCiAgICAgZ3N0YXR1cyA9IG1jYV9yZG1zcihNU1JfSUEzMl9NQ0dfU1RBVFVTKTsKICAgICBp
ZiAoKGdzdGF0dXMgJiBNQ0dfU1RBVFVTX01DSVApICE9IDApIHsKICAgICAgICAgbWNlX3ByaW50
ayhNQ0VfQ1JJVElDQUwsICJNQ0U6IENsZWFyIE1DSVBAIGxhc3Qgc3RlcCIpOwotICAgICAgICBt
Y2Ffd3Jtc3IoTVNSX0lBMzJfTUNHX1NUQVRVUywgZ3N0YXR1cyAmIH5NQ0dfU1RBVFVTX01DSVAp
OworICAgICAgICBpZiAoIGJvb3RfY3B1X2RhdGEueDg2X3ZlbmRvciA9PSBYODZfVkVORE9SX0lO
VEVMICkKKyAgICAgICAgICAgIC8qCisgICAgICAgICAgICAgKiBJbnRlbCBTRE0gMzogQW4gYXR0
ZW1wdCB0byB3cml0ZSB0byBJQTMyX01DR19TVEFUVVMKKyAgICAgICAgICAgICAqIHdpdGggYW55
IHZhbHVlIG90aGVyIHRoYW4gMCB3b3VsZCByZXN1bHQgaW4gI0dQLgorICAgICAgICAgICAgICov
CisgICAgICAgICAgICBtY2Ffd3Jtc3IoTVNSX0lBMzJfTUNHX1NUQVRVUywgMCk7CisgICAgICAg
IGVsc2UKKyAgICAgICAgICAgIG1jYV93cm1zcihNU1JfSUEzMl9NQ0dfU1RBVFVTLCBnc3RhdHVz
ICYgfk1DR19TVEFUVVNfTUNJUCk7CiAgICAgfQogICAgIG1jZV9iYXJyaWVyX2V4aXQoJm1jZV90
cmFwX2Jhcik7CiAKLS0gCjIuMTAuMQoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fX19fClhlbi1kZXZlbCBtYWlsaW5nIGxpc3QKWGVuLWRldmVsQGxpc3RzLnhl
bi5vcmcKaHR0cHM6Ly9saXN0cy54ZW4ub3JnL3hlbi1kZXZlbAo=