From mboxrd@z Thu Jan 1 00:00:00 1970 From: Haozhong Zhang Subject: Re: [PATCH 05/19] x86/mce: merge loops to get Intel extended MC MSR Date: Mon, 20 Feb 2017 09:11:08 +0800 Message-ID: <20170220011108.cxywz6qngpgpacwt@hz-desktop> References: <20170217063936.13208-1-haozhong.zhang@intel.com> <20170217063936.13208-6-haozhong.zhang@intel.com> <58A6D747020000780013B2A0@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <58A6D747020000780013B2A0@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: Jan Beulich Cc: Andrew Cooper , Christoph Egger , xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org T24gMDIvMTcvMTcgMDI6NTggLTA3MDAsIEphbiBCZXVsaWNoIHdyb3RlOgo+Pj4+IE9uIDE3LjAy LjE3IGF0IDA3OjM5LCA8aGFvemhvbmcuemhhbmdAaW50ZWwuY29tPiB3cm90ZToKPj4gVGhlIHNl Y29uZCBsb29wIHRoYXQgZ2V0cyBNU1JfSUEzMl9NQ0dfUjggdG8gTVNSX0lBMzJfTUNHX1IxNSB3 YXMKPj4gc3Vycm91bmRlZCBieSAnI2lmZGVmIF9fWDg2XzY0X18gLi4uICNlbmRpZicgYW5kIGhh ZCB0byBiZSBzZXBlcmF0ZWQKPj4gZnJvbSB0aGUgZmlyc3QgbG9vcCB0aGF0IGdldHMgTVNSX0lB MzJfTUNHX0VBWCB0byBNU1JfSUEzMl9NQ0dfTUlTQy4KPj4gQmVjYXVzZSBYZW4gaGFkIGRyb3Bw ZWQgc3VwcG9ydCBmb3IgMzItYml0IHg4NiBob3N0LCB0aGVzZSB0d28gbG9vcHMKPj4gY2FuIGJl IG1lcmdlZCBub3cuCj4KPk5vLCB0aGV5IGNhbid0IC0gdGhlIG51bWJlciBzcGFjZXMgYXJlbid0 IGNvbnRpZ3VvdXMuCj4KU29ycnksIG15IG1pc3Rha2UuIEknbGwgZHJvcCB0aGlzIG9uZS4KClRo YW5rcywKSGFvemhvbmcKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fClhlbi1kZXZlbCBtYWlsaW5nIGxpc3QKWGVuLWRldmVsQGxpc3RzLnhlbi5vcmcKaHR0 cHM6Ly9saXN0cy54ZW4ub3JnL3hlbi1kZXZlbAo=