From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH 3/9] pinctrl: sunxi: add support for R40 pinctrl Date: Tue, 21 Feb 2017 15:02:33 -0800 Message-ID: <20170221230233.2o4idjwybmkkakcs@lukather> References: <20170217173722.6477-1-icenowy@aosc.xyz> <20170217173722.6477-4-icenowy@aosc.xyz> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="haxkjxj4vh5e3bal" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20170217173722.6477-4-icenowy-ymACFijhrKM@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Icenowy Zheng Cc: Chen-Yu Tsai , Kishon Vijay Abraham I , Linus Walleij , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: linux-gpio@vger.kernel.org --haxkjxj4vh5e3bal Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Sat, Feb 18, 2017 at 01:37:16AM +0800, Icenowy Zheng wrote: > Allwinner R40 have a pin controller similar to A20, only added 8-bit > eMMC function to mmc2 at PC bank. > > Add support for it in the already renamed sunxi-a20-r40 driver via > variant framework. > > Signed-off-by: Icenowy Zheng I think a prerequisite would be to merge A10 as well (possibly even the other way around: A20 and R40 into the A10 driver). Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --haxkjxj4vh5e3bal-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Tue, 21 Feb 2017 15:02:33 -0800 From: Maxime Ripard To: Icenowy Zheng Subject: Re: [PATCH 3/9] pinctrl: sunxi: add support for R40 pinctrl Message-ID: <20170221230233.2o4idjwybmkkakcs@lukather> References: <20170217173722.6477-1-icenowy@aosc.xyz> <20170217173722.6477-4-icenowy@aosc.xyz> MIME-Version: 1.0 In-Reply-To: <20170217173722.6477-4-icenowy@aosc.xyz> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linus Walleij , linux-sunxi@googlegroups.com, Kishon Vijay Abraham I , linux-gpio@vger.kernel.org, Chen-Yu Tsai , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: multipart/mixed; boundary="===============8111783796037153037==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+mturquette=baylibre.com@lists.infradead.org List-ID: --===============8111783796037153037== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="haxkjxj4vh5e3bal" Content-Disposition: inline --haxkjxj4vh5e3bal Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, Feb 18, 2017 at 01:37:16AM +0800, Icenowy Zheng wrote: > Allwinner R40 have a pin controller similar to A20, only added 8-bit > eMMC function to mmc2 at PC bank. >=20 > Add support for it in the already renamed sunxi-a20-r40 driver via > variant framework. >=20 > Signed-off-by: Icenowy Zheng I think a prerequisite would be to merge A10 as well (possibly even the other way around: A20 and R40 into the A10 driver). Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --haxkjxj4vh5e3bal Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAEBCAAGBQJYrMcFAAoJEBx+YmzsjxAgo6MP/0w3Z03q1sxqxWVJYWCWTFuk wePHnb61OPLqRq0jUEZ/vAEynFr1FLIqdkiimkcn3y7oGrb3nSORzdrJBglR3J2X lE9bU5iQ5zDLBdEktR4G18DyCDdkkhxFwNh1RetaKsC8PypYqLD7jLRrAUYz0Cmc wdWjtahsWGL2A4ER1UXPff3PCLkqOjwWWWs3lLzhyD7NpAQ0pje03quLDVujqplr ip8Te9rv99JJxuEnMVjMaHunACm2WOZKynT+uO6GmyeAE1d1s+f9fDh6XSmXzBcr JXZK8CgXyfWnp1IKpBuKCJlQ/03eGCqeywIT+nfmEQjxO87E/16MHO2MSbEMVoqU SIY1VvGk8/8pk/1Oml+CnQ/J2Hip3rfc21WXpw0tC4Z9Y7mGGq5NitiTbnckIPp5 Zgsg9In8TaAbvlxBSdklLH8rtl1uXCisMICAldGCjIsy1/q3kASwKYYK7yy7EchT cz7c859ECMAMnH92UyJ833r2ej30jwZIZKFh/tc+gLq1CE6XsB4Pc4wshBpGO6i1 Q5QGuG3tRsWkF1JfVeidLsOfE0YuWulWa5tO5MwzM49BkkCmoMqDGhW5X637KjBn ospK1/KDkOUyzFYxdxg28o+hNybDLQzYr1xEfEMgihet+TJKhAXNfttNVGiC9wnw H1zkjDHW+vUQQxxIW9Vp =+uEd -----END PGP SIGNATURE----- --haxkjxj4vh5e3bal-- --===============8111783796037153037== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============8111783796037153037==-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Tue, 21 Feb 2017 15:02:33 -0800 Subject: [PATCH 3/9] pinctrl: sunxi: add support for R40 pinctrl In-Reply-To: <20170217173722.6477-4-icenowy@aosc.xyz> References: <20170217173722.6477-1-icenowy@aosc.xyz> <20170217173722.6477-4-icenowy@aosc.xyz> Message-ID: <20170221230233.2o4idjwybmkkakcs@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Sat, Feb 18, 2017 at 01:37:16AM +0800, Icenowy Zheng wrote: > Allwinner R40 have a pin controller similar to A20, only added 8-bit > eMMC function to mmc2 at PC bank. > > Add support for it in the already renamed sunxi-a20-r40 driver via > variant framework. > > Signed-off-by: Icenowy Zheng I think a prerequisite would be to merge A10 as well (possibly even the other way around: A20 and R40 into the A10 driver). Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: