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Subject: Re: [PATCH v2] gpio: pl061: use all specified IRQs for chained
 handler
Date: Thu, 23 Feb 2017 13:58:01 +0100
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To: Linus Walleij <linus.walleij@linaro.org>
Cc: Alexander Sverdlin <alexander.sverdlin@nokia.com>, Marc Zyngier <marc.zyngier@arm.com>, Krzysztof Adamski <krzysztof.adamski@nokia.com>, Alexandre Courbot <gnurou@gmail.com>, "linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>

On Feb 23, 2017 10:45, Linus Walleij wrote:
> On Wed, Feb 22, 2017 at 1:57 PM, Alexander Sverdlin
> <alexander.sverdlin@nokia.com> wrote:
> 
> >> - If the component has 8 IRQ lines, create a hierarchical IRQdomain
> >>   and chip using a gpiolib core helper.
> >
> > This was an option of course, the only this is, PL061 spec says, there is
> > GPIOINTR and if someone has forgot it, we can support it with a quirk.
> 
> I don't know about that. The PL061 manual says:
> 
> "The contents of this register are made available externally through the
> intra-chip (or on-chip) GPIOMIS[7:0] signals."
> 
> They don't say why, but it is reasonable to assume that this is an
> either-or not both-and integration point.
> 
> EITHER you route GPIOMIS[7:0] to individual IRQ lines to the CPU
> OR you route GPIOINTR to the CPU.

On page 2-10, 2.3.4 you can read:

"a single interrupt output GPIOINTR and/or the individual interrupts can be 
sent to the interrupt controller."

Also see figure 2-1, 4-2.

Does it not says that there are two independent options available?

-- 
Best regards
Sławomir Stępień