From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751656AbdBXM46 (ORCPT ); Fri, 24 Feb 2017 07:56:58 -0500 Received: from dougal.metanate.com ([90.155.101.14]:47940 "EHLO metanate.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751320AbdBXMz1 (ORCPT ); Fri, 24 Feb 2017 07:55:27 -0500 From: John Keeping To: Mark Yao Cc: Chris Zhong , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Paul , John Keeping Subject: [PATCH v4 17/23] drm/rockchip: dw-mipi-dsi: improve PLL configuration Date: Fri, 24 Feb 2017 12:55:00 +0000 Message-Id: <20170224125506.21533-18-john@metanate.com> X-Mailer: git-send-email 2.12.0.rc0.230.gf625d4cdb9.dirty In-Reply-To: <20170224125506.21533-1-john@metanate.com> References: <20170224125506.21533-1-john@metanate.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The multiplication ratio for the PLL is required to be even due to the use of a "by 2 pre-scaler". Currently we are likely to end up with an odd multiplier even though there is an equivalent set of parameters with an even multiplier. For example, using the 324MHz bit rate with a reference clock of 24MHz we end up with M = 27, N = 2 whereas the example in the PHY databook gives M = 54, N = 4 for this bit rate and reference clock. By walking down through the available multiplier instead of up we are more likely to hit an even multiplier. With the above example we do now get M = 54, N = 4 as given by the databook. While doing this, change the loop limits to encode the actual limits on the divisor, which are: 40MHz >= (pllref / N) >= 5MHz Signed-off-by: John Keeping Reviewed-by: Sean Paul --- v4: - Add a comment explaining the limits so that it can be understood without finding the commit message above - Add Sean's Reviewed-by Unchanged in v3 Unchanged in v2 --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 9b6a60deb69e..e6b52c7cb5e3 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -518,7 +518,18 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC); tmp = pllref; - for (i = 1; i < 6; i++) { + /* + * The limits on the PLL divisor are: + * + * 5MHz <= (pllref / n) <= 40MHz + * + * we walk over these values in descreasing order so that if we hit + * an exact match for target_mbps it is more likely that "m" will be + * even. + * + * TODO: ensure that "m" is even after this loop. + */ + for (i = pllref / 5; i > (pllref / 40); i--) { pre = pllref / i; if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) { tmp = target_mbps % pre; -- 2.12.0.rc0.230.gf625d4cdb9.dirty From mboxrd@z Thu Jan 1 00:00:00 1970 From: John Keeping Subject: [PATCH v4 17/23] drm/rockchip: dw-mipi-dsi: improve PLL configuration Date: Fri, 24 Feb 2017 12:55:00 +0000 Message-ID: <20170224125506.21533-18-john@metanate.com> References: <20170224125506.21533-1-john@metanate.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20170224125506.21533-1-john@metanate.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Mark Yao Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org List-Id: linux-rockchip.vger.kernel.org VGhlIG11bHRpcGxpY2F0aW9uIHJhdGlvIGZvciB0aGUgUExMIGlzIHJlcXVpcmVkIHRvIGJlIGV2 ZW4gZHVlIHRvIHRoZQp1c2Ugb2YgYSAiYnkgMiBwcmUtc2NhbGVyIi4gIEN1cnJlbnRseSB3ZSBh cmUgbGlrZWx5IHRvIGVuZCB1cCB3aXRoIGFuCm9kZCBtdWx0aXBsaWVyIGV2ZW4gdGhvdWdoIHRo ZXJlIGlzIGFuIGVxdWl2YWxlbnQgc2V0IG9mIHBhcmFtZXRlcnMgd2l0aAphbiBldmVuIG11bHRp cGxpZXIuCgpGb3IgZXhhbXBsZSwgdXNpbmcgdGhlIDMyNE1IeiBiaXQgcmF0ZSB3aXRoIGEgcmVm ZXJlbmNlIGNsb2NrIG9mIDI0TUh6CndlIGVuZCB1cCB3aXRoIE0gPSAyNywgTiA9IDIgd2hlcmVh cyB0aGUgZXhhbXBsZSBpbiB0aGUgUEhZIGRhdGFib29rCmdpdmVzIE0gPSA1NCwgTiA9IDQgZm9y IHRoaXMgYml0IHJhdGUgYW5kIHJlZmVyZW5jZSBjbG9jay4KCkJ5IHdhbGtpbmcgZG93biB0aHJv dWdoIHRoZSBhdmFpbGFibGUgbXVsdGlwbGllciBpbnN0ZWFkIG9mIHVwIHdlIGFyZQptb3JlIGxp a2VseSB0byBoaXQgYW4gZXZlbiBtdWx0aXBsaWVyLiAgV2l0aCB0aGUgYWJvdmUgZXhhbXBsZSB3 ZSBkbyBub3cKZ2V0IE0gPSA1NCwgTiA9IDQgYXMgZ2l2ZW4gYnkgdGhlIGRhdGFib29rLgoKV2hp bGUgZG9pbmcgdGhpcywgY2hhbmdlIHRoZSBsb29wIGxpbWl0cyB0byBlbmNvZGUgdGhlIGFjdHVh bCBsaW1pdHMgb24KdGhlIGRpdmlzb3IsIHdoaWNoIGFyZToKCgk0ME1IeiA+PSAocGxscmVmIC8g TikgPj0gNU1IegoKU2lnbmVkLW9mZi1ieTogSm9obiBLZWVwaW5nIDxqb2huQG1ldGFuYXRlLmNv bT4KUmV2aWV3ZWQtYnk6IFNlYW4gUGF1bCA8c2VhbnBhdWxAY2hyb21pdW0ub3JnPgotLS0KdjQ6 Ci0gQWRkIGEgY29tbWVudCBleHBsYWluaW5nIHRoZSBsaW1pdHMgc28gdGhhdCBpdCBjYW4gYmUg dW5kZXJzdG9vZAogIHdpdGhvdXQgZmluZGluZyB0aGUgY29tbWl0IG1lc3NhZ2UgYWJvdmUKLSBB ZGQgU2VhbidzIFJldmlld2VkLWJ5ClVuY2hhbmdlZCBpbiB2MwpVbmNoYW5nZWQgaW4gdjIKLS0t CiBkcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvZHctbWlwaS1kc2kuYyB8IDEzICsrKysrKysrKysr Ky0KIDEgZmlsZSBjaGFuZ2VkLCAxMiBpbnNlcnRpb25zKCspLCAxIGRlbGV0aW9uKC0pCgpkaWZm IC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL2R3LW1pcGktZHNpLmMgYi9kcml2ZXJz L2dwdS9kcm0vcm9ja2NoaXAvZHctbWlwaS1kc2kuYwppbmRleCA5YjZhNjBkZWI2OWUuLmU2YjUy YzdjYjVlMyAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL2R3LW1pcGktZHNp LmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL2R3LW1pcGktZHNpLmMKQEAgLTUxOCw3 ICs1MTgsMTggQEAgc3RhdGljIGludCBkd19taXBpX2RzaV9nZXRfbGFuZV9icHMoc3RydWN0IGR3 X21pcGlfZHNpICpkc2ksCiAJcGxscmVmID0gRElWX1JPVU5EX1VQKGNsa19nZXRfcmF0ZShkc2kt PnBsbHJlZl9jbGspLCBVU0VDX1BFUl9TRUMpOwogCXRtcCA9IHBsbHJlZjsKIAotCWZvciAoaSA9 IDE7IGkgPCA2OyBpKyspIHsKKwkvKgorCSAqIFRoZSBsaW1pdHMgb24gdGhlIFBMTCBkaXZpc29y IGFyZToKKwkgKgorCSAqCTVNSHogPD0gKHBsbHJlZiAvIG4pIDw9IDQwTUh6CisJICoKKwkgKiB3 ZSB3YWxrIG92ZXIgdGhlc2UgdmFsdWVzIGluIGRlc2NyZWFzaW5nIG9yZGVyIHNvIHRoYXQgaWYg d2UgaGl0CisJICogYW4gZXhhY3QgbWF0Y2ggZm9yIHRhcmdldF9tYnBzIGl0IGlzIG1vcmUgbGlr ZWx5IHRoYXQgIm0iIHdpbGwgYmUKKwkgKiBldmVuLgorCSAqCisJICogVE9ETzogZW5zdXJlIHRo YXQgIm0iIGlzIGV2ZW4gYWZ0ZXIgdGhpcyBsb29wLgorCSAqLworCWZvciAoaSA9IHBsbHJlZiAv IDU7IGkgPiAocGxscmVmIC8gNDApOyBpLS0pIHsKIAkJcHJlID0gcGxscmVmIC8gaTsKIAkJaWYg KCh0bXAgPiAodGFyZ2V0X21icHMgJSBwcmUpKSAmJiAodGFyZ2V0X21icHMgLyBwcmUgPCA1MTIp KSB7CiAJCQl0bXAgPSB0YXJnZXRfbWJwcyAlIHByZTsKLS0gCjIuMTIuMC5yYzAuMjMwLmdmNjI1 ZDRjZGI5LmRpcnR5CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5v cmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2 ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: john@metanate.com (John Keeping) Date: Fri, 24 Feb 2017 12:55:00 +0000 Subject: [PATCH v4 17/23] drm/rockchip: dw-mipi-dsi: improve PLL configuration In-Reply-To: <20170224125506.21533-1-john@metanate.com> References: <20170224125506.21533-1-john@metanate.com> Message-ID: <20170224125506.21533-18-john@metanate.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The multiplication ratio for the PLL is required to be even due to the use of a "by 2 pre-scaler". Currently we are likely to end up with an odd multiplier even though there is an equivalent set of parameters with an even multiplier. For example, using the 324MHz bit rate with a reference clock of 24MHz we end up with M = 27, N = 2 whereas the example in the PHY databook gives M = 54, N = 4 for this bit rate and reference clock. By walking down through the available multiplier instead of up we are more likely to hit an even multiplier. With the above example we do now get M = 54, N = 4 as given by the databook. While doing this, change the loop limits to encode the actual limits on the divisor, which are: 40MHz >= (pllref / N) >= 5MHz Signed-off-by: John Keeping Reviewed-by: Sean Paul --- v4: - Add a comment explaining the limits so that it can be understood without finding the commit message above - Add Sean's Reviewed-by Unchanged in v3 Unchanged in v2 --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 9b6a60deb69e..e6b52c7cb5e3 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -518,7 +518,18 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC); tmp = pllref; - for (i = 1; i < 6; i++) { + /* + * The limits on the PLL divisor are: + * + * 5MHz <= (pllref / n) <= 40MHz + * + * we walk over these values in descreasing order so that if we hit + * an exact match for target_mbps it is more likely that "m" will be + * even. + * + * TODO: ensure that "m" is even after this loop. + */ + for (i = pllref / 5; i > (pllref / 40); i--) { pre = pllref / i; if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) { tmp = target_mbps % pre; -- 2.12.0.rc0.230.gf625d4cdb9.dirty