From: Gavin Shan <gwshan@linux.vnet.ibm.com>
To: Alexey Kardashevskiy <aik@ozlabs.ru>
Cc: linuxppc-dev@lists.ozlabs.org,
Gavin Shan <gwshan@linux.vnet.ibm.com>,
Russell Currey <ruscur@russell.cc>,
David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [PATCH kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested
Date: Mon, 27 Feb 2017 11:53:03 +1100 [thread overview]
Message-ID: <20170227005303.GA4780@gwshan> (raw)
In-Reply-To: <20170222044359.3663-1-aik@ozlabs.ru>
On Wed, Feb 22, 2017 at 03:43:59PM +1100, Alexey Kardashevskiy wrote:
>The IODA2 specification says that a 64 DMA address cannot use top 4 bits
>(3 are reserved and one is a "TVE select"); bottom page_shift bits
>cannot be used for multilevel table addressing either.
>
>The existing IODA2 table allocation code aligns the minimum TCE table
>size to PAGE_SIZE so in the case of 64K system pages and 4K IOMMU pages,
>we have 64-4-12=48 bits. Since 64K page stores 8192 TCEs, i.e. needs
>13 bits, the maximum number of levels is 48/13 = 3 so we physically
>cannot address more and EEH happens on DMA accesses.
>
>This adds a check that too many levels were requested.
>
>It is still possible to have 5 levels in the case of 4K system page size.
>
>Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>---
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
next prev parent reply other threads:[~2017-02-27 0:54 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-22 4:43 [PATCH kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested Alexey Kardashevskiy
2017-02-27 0:53 ` Gavin Shan [this message]
2017-02-27 11:00 ` Michael Ellerman
2017-02-28 0:54 ` Alexey Kardashevskiy
2017-03-05 23:03 ` Benjamin Herrenschmidt
2017-03-06 1:28 ` Alexey Kardashevskiy
2017-03-06 3:36 ` Benjamin Herrenschmidt
2017-03-06 4:02 ` Alexey Kardashevskiy
2017-03-14 11:45 ` [kernel] " Michael Ellerman
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