From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753406AbdCBTDc (ORCPT ); Thu, 2 Mar 2017 14:03:32 -0500 Received: from bh-25.webhostbox.net ([208.91.199.152]:33023 "EHLO bh-25.webhostbox.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751735AbdCBTD2 (ORCPT ); Thu, 2 Mar 2017 14:03:28 -0500 Date: Thu, 2 Mar 2017 09:42:24 -0800 From: Guenter Roeck To: Alexandre Belloni Cc: Wim Van Sebroeck , Nicolas Ferre , Wenyou.Yang@microchip.com, linux-watchdog@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/4] watchdog: sama5d4: fix race condition Message-ID: <20170302174224.GC28554@roeck-us.net> References: <20170302173114.28508-1-alexandre.belloni@free-electrons.com> <20170302173114.28508-3-alexandre.belloni@free-electrons.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20170302173114.28508-3-alexandre.belloni@free-electrons.com> User-Agent: Mutt/1.5.24 (2015-08-30) X-Authenticated_sender: guenter@roeck-us.net X-OutGoing-Spam-Status: No, score=-1.0 X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - bh-25.webhostbox.net X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - roeck-us.net X-Get-Message-Sender-Via: bh-25.webhostbox.net: authenticated_id: guenter@roeck-us.net X-Authenticated-Sender: bh-25.webhostbox.net: guenter@roeck-us.net X-Source: X-Source-Args: X-Source-Dir: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 02, 2017 at 06:31:12PM +0100, Alexandre Belloni wrote: > WDT_MR and WDT_CR must not updated within three slow clock periods after > the last ping (write to WDT_CR or WDT_MR). Ensure enough time has elapsed > before writing those registers. > wdt_write() waits for 4 periods to ensure at least 3 edges are seen by the > IP. > Would it be possible to use min_hw_heartbeat_ms for this purpose ? Thanks, Guenter > Signed-off-by: Alexandre Belloni > --- > drivers/watchdog/sama5d4_wdt.c | 33 +++++++++++++++++++++++++++++---- > 1 file changed, 29 insertions(+), 4 deletions(-) > > diff --git a/drivers/watchdog/sama5d4_wdt.c b/drivers/watchdog/sama5d4_wdt.c > index 5cee20caca78..362fd229786d 100644 > --- a/drivers/watchdog/sama5d4_wdt.c > +++ b/drivers/watchdog/sama5d4_wdt.c > @@ -6,6 +6,7 @@ > * Licensed under GPLv2. > */ > > +#include > #include > #include > #include > @@ -29,6 +30,7 @@ struct sama5d4_wdt { > struct watchdog_device wdd; > void __iomem *reg_base; > u32 mr; > + unsigned long last_ping; > }; > > static int wdt_timeout = WDT_DEFAULT_TIMEOUT; > @@ -49,8 +51,29 @@ MODULE_PARM_DESC(nowayout, > #define wdt_read(wdt, field) \ > readl_relaxed((wdt)->reg_base + (field)) > > -#define wdt_write(wtd, field, val) \ > - writel_relaxed((val), (wdt)->reg_base + (field)) > +/* 4 slow clock periods is 4/32768 = 122.07µs*/ > +#define WDT_DELAY usecs_to_jiffies(123) > + > +static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val) > +{ > + /* > + * WDT_CR and WDT_MR must not be modified within three slow clock > + * periods following a restart of the watchdog performed by a write > + * access in WDT_CR. > + */ > + while (time_before(jiffies, wdt->last_ping + WDT_DELAY)) > + usleep_range(30, 125); > + writel_relaxed(val, wdt->reg_base + field); > + wdt->last_ping = jiffies; > +} > + > +static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val) > +{ > + if (time_before(jiffies, wdt->last_ping + WDT_DELAY)) > + udelay(123); > + writel_relaxed(val, wdt->reg_base + field); > + wdt->last_ping = jiffies; > +} > > static int sama5d4_wdt_start(struct watchdog_device *wdd) > { > @@ -164,11 +187,12 @@ static int sama5d4_wdt_init(struct sama5d4_wdt *wdt) > * Else, we have to disable it properly. > */ > if (wdt_enabled) { > - wdt_write(wdt, AT91_WDT_MR, wdt->mr); > + wdt_write_nosleep(wdt, AT91_WDT_MR, wdt->mr); > } else { > reg = wdt_read(wdt, AT91_WDT_MR); > if (!(reg & AT91_WDT_WDDIS)) > - wdt_write(wdt, AT91_WDT_MR, reg | AT91_WDT_WDDIS); > + wdt_write_nosleep(wdt, AT91_WDT_MR, > + reg | AT91_WDT_WDDIS); > } > return 0; > } > @@ -193,6 +217,7 @@ static int sama5d4_wdt_probe(struct platform_device *pdev) > wdd->ops = &sama5d4_wdt_ops; > wdd->min_timeout = MIN_WDT_TIMEOUT; > wdd->max_timeout = MAX_WDT_TIMEOUT; > + wdt->last_ping = jiffies; > > watchdog_set_drvdata(wdd, wdt); > > -- > 2.11.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@roeck-us.net (Guenter Roeck) Date: Thu, 2 Mar 2017 09:42:24 -0800 Subject: [PATCH 2/4] watchdog: sama5d4: fix race condition In-Reply-To: <20170302173114.28508-3-alexandre.belloni@free-electrons.com> References: <20170302173114.28508-1-alexandre.belloni@free-electrons.com> <20170302173114.28508-3-alexandre.belloni@free-electrons.com> Message-ID: <20170302174224.GC28554@roeck-us.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Mar 02, 2017 at 06:31:12PM +0100, Alexandre Belloni wrote: > WDT_MR and WDT_CR must not updated within three slow clock periods after > the last ping (write to WDT_CR or WDT_MR). Ensure enough time has elapsed > before writing those registers. > wdt_write() waits for 4 periods to ensure at least 3 edges are seen by the > IP. > Would it be possible to use min_hw_heartbeat_ms for this purpose ? Thanks, Guenter > Signed-off-by: Alexandre Belloni > --- > drivers/watchdog/sama5d4_wdt.c | 33 +++++++++++++++++++++++++++++---- > 1 file changed, 29 insertions(+), 4 deletions(-) > > diff --git a/drivers/watchdog/sama5d4_wdt.c b/drivers/watchdog/sama5d4_wdt.c > index 5cee20caca78..362fd229786d 100644 > --- a/drivers/watchdog/sama5d4_wdt.c > +++ b/drivers/watchdog/sama5d4_wdt.c > @@ -6,6 +6,7 @@ > * Licensed under GPLv2. > */ > > +#include > #include > #include > #include > @@ -29,6 +30,7 @@ struct sama5d4_wdt { > struct watchdog_device wdd; > void __iomem *reg_base; > u32 mr; > + unsigned long last_ping; > }; > > static int wdt_timeout = WDT_DEFAULT_TIMEOUT; > @@ -49,8 +51,29 @@ MODULE_PARM_DESC(nowayout, > #define wdt_read(wdt, field) \ > readl_relaxed((wdt)->reg_base + (field)) > > -#define wdt_write(wtd, field, val) \ > - writel_relaxed((val), (wdt)->reg_base + (field)) > +/* 4 slow clock periods is 4/32768 = 122.07?s*/ > +#define WDT_DELAY usecs_to_jiffies(123) > + > +static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val) > +{ > + /* > + * WDT_CR and WDT_MR must not be modified within three slow clock > + * periods following a restart of the watchdog performed by a write > + * access in WDT_CR. > + */ > + while (time_before(jiffies, wdt->last_ping + WDT_DELAY)) > + usleep_range(30, 125); > + writel_relaxed(val, wdt->reg_base + field); > + wdt->last_ping = jiffies; > +} > + > +static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val) > +{ > + if (time_before(jiffies, wdt->last_ping + WDT_DELAY)) > + udelay(123); > + writel_relaxed(val, wdt->reg_base + field); > + wdt->last_ping = jiffies; > +} > > static int sama5d4_wdt_start(struct watchdog_device *wdd) > { > @@ -164,11 +187,12 @@ static int sama5d4_wdt_init(struct sama5d4_wdt *wdt) > * Else, we have to disable it properly. > */ > if (wdt_enabled) { > - wdt_write(wdt, AT91_WDT_MR, wdt->mr); > + wdt_write_nosleep(wdt, AT91_WDT_MR, wdt->mr); > } else { > reg = wdt_read(wdt, AT91_WDT_MR); > if (!(reg & AT91_WDT_WDDIS)) > - wdt_write(wdt, AT91_WDT_MR, reg | AT91_WDT_WDDIS); > + wdt_write_nosleep(wdt, AT91_WDT_MR, > + reg | AT91_WDT_WDDIS); > } > return 0; > } > @@ -193,6 +217,7 @@ static int sama5d4_wdt_probe(struct platform_device *pdev) > wdd->ops = &sama5d4_wdt_ops; > wdd->min_timeout = MIN_WDT_TIMEOUT; > wdd->max_timeout = MAX_WDT_TIMEOUT; > + wdt->last_ping = jiffies; > > watchdog_set_drvdata(wdd, wdt); > > -- > 2.11.0 >