From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751810AbdCBWxD (ORCPT ); Thu, 2 Mar 2017 17:53:03 -0500 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:35245 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751623AbdCBWwl (ORCPT ); Thu, 2 Mar 2017 17:52:41 -0500 From: Chris Packham To: linux-arm-kernel@lists.infradead.org, gregory.clement@free-electrons.com Cc: Chris Packham , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Rob Herring , Mark Rutland , Russell King , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM: dts: mvebu: remove unnecessary PCI range from 98dx3236 Date: Fri, 3 Mar 2017 11:42:39 +1300 Message-Id: <20170302224239.10062-1-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.11.0.24.ge6920cf Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Marvell 98dx3236 SoC only has a single PCIe x1 interface. The "Port 0.1 MEM" range was errantly kept when creating a specific dts for the SoC. Signed-off-by: Chris Packham --- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index f6a03dcee5ef..0e63f927c73d 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -95,8 +95,7 @@ ranges = <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>; + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; pcie1: pcie@1,0 { device_type = "pci"; -- 2.11.0.24.ge6920cf From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Packham Subject: [PATCH] ARM: dts: mvebu: remove unnecessary PCI range from 98dx3236 Date: Fri, 3 Mar 2017 11:42:39 +1300 Message-ID: <20170302224239.10062-1-chris.packham@alliedtelesis.co.nz> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: linux-arm-kernel@lists.infradead.org, gregory.clement@free-electrons.com Cc: Mark Rutland , Andrew Lunn , Jason Cooper , devicetree@vger.kernel.org, Russell King , Rob Herring , linux-kernel@vger.kernel.org, Chris Packham , Sebastian Hesselbarth List-Id: devicetree@vger.kernel.org The Marvell 98dx3236 SoC only has a single PCIe x1 interface. The "Port 0.1 MEM" range was errantly kept when creating a specific dts for the SoC. Signed-off-by: Chris Packham --- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index f6a03dcee5ef..0e63f927c73d 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -95,8 +95,7 @@ ranges = <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>; + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; pcie1: pcie@1,0 { device_type = "pci"; -- 2.11.0.24.ge6920cf From mboxrd@z Thu Jan 1 00:00:00 1970 From: chris.packham@alliedtelesis.co.nz (Chris Packham) Date: Fri, 3 Mar 2017 11:42:39 +1300 Subject: [PATCH] ARM: dts: mvebu: remove unnecessary PCI range from 98dx3236 Message-ID: <20170302224239.10062-1-chris.packham@alliedtelesis.co.nz> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The Marvell 98dx3236 SoC only has a single PCIe x1 interface. The "Port 0.1 MEM" range was errantly kept when creating a specific dts for the SoC. Signed-off-by: Chris Packham --- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index f6a03dcee5ef..0e63f927c73d 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -95,8 +95,7 @@ ranges = <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>; + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; pcie1: pcie at 1,0 { device_type = "pci"; -- 2.11.0.24.ge6920cf