* [PATCH v2 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs
@ 2017-03-15 17:28 ` Icenowy Zheng
0 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-15 17:28 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
Allwinner SoCs after sun6i-a31 nearly all have a R_CCU in PRCM part.
(V3s and R40 do not have it, as they have even no PRCM)
This patch adds support for the ones on H3/A64.
Some clock/reset values are reserved for easier extending the support to
A31/A23, but for this I think some changes to the PRCM MFD should be made,
see [1] (Although this is only a sketch).
The r_pio device node is also added for A64, as the driver is already
merged, and its depends (r_ccu) is now met.
[1] https://github.com/wens/linux/commits/sunxi-ng-prcm
Icenowy Zheng (5):
dt-bindings: update device tree binding for Allwinner PRCM CCUs
clk: sunxi-ng: add support for PRCM CCUs
arm64: allwinner: a64: add r_ccu node
ARM: sun8i: h3: switch apb0-related clocks to r_ccu
arm64: allwinner: a64: add R_PIO pinctrl node
.../devicetree/bindings/clock/sunxi-ccu.txt | 18 +-
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 46 ++---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 30 +++
drivers/clk/sunxi-ng/Kconfig | 6 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-r.c | 211 +++++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun8i-r.h | 27 +++
include/dt-bindings/clock/sun8i-r-ccu.h | 59 ++++++
include/dt-bindings/reset/sun8i-r-ccu.h | 53 ++++++
9 files changed, 419 insertions(+), 32 deletions(-)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.h
create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h
--
2.12.0
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs
@ 2017-03-15 17:28 ` Icenowy Zheng
0 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-15 17:28 UTC (permalink / raw)
To: linux-arm-kernel
Allwinner SoCs after sun6i-a31 nearly all have a R_CCU in PRCM part.
(V3s and R40 do not have it, as they have even no PRCM)
This patch adds support for the ones on H3/A64.
Some clock/reset values are reserved for easier extending the support to
A31/A23, but for this I think some changes to the PRCM MFD should be made,
see [1] (Although this is only a sketch).
The r_pio device node is also added for A64, as the driver is already
merged, and its depends (r_ccu) is now met.
[1] https://github.com/wens/linux/commits/sunxi-ng-prcm
Icenowy Zheng (5):
dt-bindings: update device tree binding for Allwinner PRCM CCUs
clk: sunxi-ng: add support for PRCM CCUs
arm64: allwinner: a64: add r_ccu node
ARM: sun8i: h3: switch apb0-related clocks to r_ccu
arm64: allwinner: a64: add R_PIO pinctrl node
.../devicetree/bindings/clock/sunxi-ccu.txt | 18 +-
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 46 ++---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 30 +++
drivers/clk/sunxi-ng/Kconfig | 6 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-r.c | 211 +++++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun8i-r.h | 27 +++
include/dt-bindings/clock/sun8i-r-ccu.h | 59 ++++++
include/dt-bindings/reset/sun8i-r-ccu.h | 53 ++++++
9 files changed, 419 insertions(+), 32 deletions(-)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.h
create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h
--
2.12.0
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
2017-03-15 17:28 ` Icenowy Zheng
@ 2017-03-15 17:28 ` Icenowy Zheng
-1 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-15 17:28 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
Many Allwinner SoCs after A31 have a CCU in PRCM block.
Give the ones on H3 and A64 compatible strings.
Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
Changes in v2:
- Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
clock for mux 3 of ar100 clk. Investgations are needed for them.)
Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 68512aa398a9..4a4addff595d 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -7,9 +7,11 @@ Required properties :
- "allwinner,sun8i-a23-ccu"
- "allwinner,sun8i-a33-ccu"
- "allwinner,sun8i-h3-ccu"
+ - "allwinner,sun8i-h3-r-ccu"
- "allwinner,sun8i-v3s-ccu"
- "allwinner,sun9i-a80-ccu"
- "allwinner,sun50i-a64-ccu"
+ - "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
- reg: Must contain the registers base address and length
@@ -20,7 +22,11 @@ Required properties :
- #clock-cells : must contain 1
- #reset-cells : must contain 1
-Example:
+For the PRCM CCUs on H3/A64, one more clock is needed:
+- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
+ not the same with losc)
+
+Example for generic CCU:
ccu: clock@01c20000 {
compatible = "allwinner,sun8i-h3-ccu";
reg = <0x01c20000 0x400>;
@@ -29,3 +35,13 @@ ccu: clock@01c20000 {
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+Example for PRCM CCU:
+r_ccu: clock@01f01400 {
+ compatible = "allwinner,sun50i-a64-r-ccu";
+ reg = <0x01f01400 0x100>;
+ clocks = <&osc24M>, <&osc32k>, <&osc32000>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
--
2.12.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
@ 2017-03-15 17:28 ` Icenowy Zheng
0 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-15 17:28 UTC (permalink / raw)
To: linux-arm-kernel
Many Allwinner SoCs after A31 have a CCU in PRCM block.
Give the ones on H3 and A64 compatible strings.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes in v2:
- Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
clock for mux 3 of ar100 clk. Investgations are needed for them.)
Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 68512aa398a9..4a4addff595d 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -7,9 +7,11 @@ Required properties :
- "allwinner,sun8i-a23-ccu"
- "allwinner,sun8i-a33-ccu"
- "allwinner,sun8i-h3-ccu"
+ - "allwinner,sun8i-h3-r-ccu"
- "allwinner,sun8i-v3s-ccu"
- "allwinner,sun9i-a80-ccu"
- "allwinner,sun50i-a64-ccu"
+ - "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
- reg: Must contain the registers base address and length
@@ -20,7 +22,11 @@ Required properties :
- #clock-cells : must contain 1
- #reset-cells : must contain 1
-Example:
+For the PRCM CCUs on H3/A64, one more clock is needed:
+- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
+ not the same with losc)
+
+Example for generic CCU:
ccu: clock at 01c20000 {
compatible = "allwinner,sun8i-h3-ccu";
reg = <0x01c20000 0x400>;
@@ -29,3 +35,13 @@ ccu: clock at 01c20000 {
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+Example for PRCM CCU:
+r_ccu: clock at 01f01400 {
+ compatible = "allwinner,sun50i-a64-r-ccu";
+ reg = <0x01f01400 0x100>;
+ clocks = <&osc24M>, <&osc32k>, <&osc32000>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
--
2.12.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 2/5] clk: sunxi-ng: add support for PRCM CCUs
2017-03-15 17:28 ` Icenowy Zheng
@ 2017-03-15 17:28 ` Icenowy Zheng
-1 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-15 17:28 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
SoCs after A31 has a clock controller module in the PRCM part.
Support the clock controller module on H5 and A64 now.
Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
Changes in v2:
- Replace all sun6i to sun8i, as this driver currently doesn't really
support sun6i(A31).
- Add osc32000 mux for ar100 clk.
- Rename some clocks.
- Add gate of TWD (Trusted Watchdog). There's no reset for TWD.
- Removed reset of PIO, which doesn't exist really.
drivers/clk/sunxi-ng/Kconfig | 6 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-r.c | 211 ++++++++++++++++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun8i-r.h | 27 ++++
include/dt-bindings/clock/sun8i-r-ccu.h | 59 +++++++++
include/dt-bindings/reset/sun8i-r-ccu.h | 53 ++++++++
6 files changed, 357 insertions(+)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.h
create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 213cf64e4fab..056752317aee 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -150,4 +150,10 @@ config SUN9I_A80_CCU
default MACH_SUN9I
depends on MACH_SUN9I || COMPILE_TEST
+config SUN8I_R_CCU
+ bool "Support for Allwinner SoCs' PRCM CCUs"
+ select SUNXI_CCU_DIV
+ select SUNXI_CCU_GATE
+ default MACH_SUN8I || (ARCH_SUNXI && ARM64)
+
endif
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 6feaac0c5600..0ec02fe14c50 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o
+obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o
obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o
obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o
obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
new file mode 100644
index 000000000000..a6884c27c098
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun8i-r.h"
+
+static const char * const ar100_parents[] = { "osc32k", "osc24M",
+ "pll-periph0", "osc32000" };
+
+static struct ccu_div ar100_clk = {
+ .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+ .mux = {
+ .shift = 16,
+ .width = 2,
+
+ .variable_prediv = {
+ .index = 2,
+ .shift = 8,
+ .width = 5,
+ },
+ },
+
+ .common = {
+ .reg = 0x00,
+ .features = CCU_FEATURE_VARIABLE_PREDIV,
+ .hw.init = CLK_HW_INIT_PARENTS("ar100",
+ ar100_parents,
+ &ccu_div_ops,
+ 0),
+ },
+};
+
+static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0);
+
+static struct ccu_div apb0_clk = {
+ .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+ .common = {
+ .reg = 0x0c,
+ .hw.init = CLK_HW_INIT("apb0",
+ "ahb0",
+ &ccu_div_ops,
+ 0),
+ },
+};
+
+static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
+ 0x28, BIT(0), 0);
+static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0",
+ 0x28, BIT(1), 0);
+static SUNXI_CCU_GATE(apb0_timer_clk, "apb0-timer", "apb0",
+ 0x28, BIT(2), 0);
+static SUNXI_CCU_GATE(apb0_rsb_clk, "apb0-rsb", "apb0",
+ 0x28, BIT(3), 0);
+static SUNXI_CCU_GATE(apb0_uart_clk, "apb0-uart", "apb0",
+ 0x28, BIT(4), 0);
+static SUNXI_CCU_GATE(apb0_i2c_clk, "apb0-i2c", "apb0",
+ 0x28, BIT(6), 0);
+static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0",
+ 0x28, BIT(7), 0);
+
+static const char * const r_mod0_default_parents[] = { "osc32K", "osc24M" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
+ r_mod0_default_parents, 0x54,
+ 0, 4, /* M */
+ 16, 2, /* P */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static struct ccu_common *sun8i_h3_r_ccu_clks[] = {
+ &ar100_clk.common,
+ &apb0_clk.common,
+ &apb0_pio_clk.common,
+ &apb0_ir_clk.common,
+ &apb0_timer_clk.common,
+ &apb0_uart_clk.common,
+ &apb0_i2c_clk.common,
+ &ir_clk.common,
+};
+
+static struct ccu_common *sun50i_a64_r_ccu_clks[] = {
+ &ar100_clk.common,
+ &apb0_clk.common,
+ &apb0_pio_clk.common,
+ &apb0_ir_clk.common,
+ &apb0_timer_clk.common,
+ &apb0_rsb_clk.common,
+ &apb0_uart_clk.common,
+ &apb0_i2c_clk.common,
+ &ir_clk.common,
+};
+
+static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = {
+ .hws = {
+ [CLK_AR100] = &ar100_clk.common.hw,
+ [CLK_AHB0] = &ahb0_clk.hw,
+ [CLK_APB0] = &apb0_clk.common.hw,
+ [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
+ [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
+ [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
+ [CLK_APB0_UART] = &apb0_uart_clk.common.hw,
+ [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
+ [CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
+ [CLK_IR] = &ir_clk.common.hw,
+ },
+ .num = CLK_NUMBER,
+};
+
+static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = {
+ .hws = {
+ [CLK_AR100] = &ar100_clk.common.hw,
+ [CLK_AHB0] = &ahb0_clk.hw,
+ [CLK_APB0] = &apb0_clk.common.hw,
+ [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
+ [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
+ [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
+ [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw,
+ [CLK_APB0_UART] = &apb0_uart_clk.common.hw,
+ [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
+ [CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
+ [CLK_IR] = &ir_clk.common.hw,
+ },
+ .num = CLK_NUMBER,
+};
+
+static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = {
+ [RST_APB0_IR] = { 0xb0, BIT(1) },
+ [RST_APB0_TIMER] = { 0xb0, BIT(2) },
+ [RST_APB0_UART] = { 0xb0, BIT(4) },
+ [RST_APB0_I2C] = { 0xb0, BIT(6) },
+};
+
+static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = {
+ [RST_APB0_IR] = { 0xb0, BIT(1) },
+ [RST_APB0_TIMER] = { 0xb0, BIT(2) },
+ [RST_APB0_RSB] = { 0xb0, BIT(3) },
+ [RST_APB0_UART] = { 0xb0, BIT(4) },
+ [RST_APB0_I2C] = { 0xb0, BIT(6) },
+};
+
+static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = {
+ .ccu_clks = sun8i_h3_r_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks),
+
+ .hw_clks = &sun8i_h3_r_hw_clks,
+
+ .resets = sun8i_h3_r_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets),
+};
+
+static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = {
+ .ccu_clks = sun50i_a64_r_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks),
+
+ .hw_clks = &sun50i_a64_r_hw_clks,
+
+ .resets = sun50i_a64_r_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets),
+};
+
+static void __init sunxi_r_ccu_init(struct device_node *node,
+ const struct sunxi_ccu_desc *desc)
+{
+ void __iomem *reg;
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (IS_ERR(reg)) {
+ pr_err("%s: Could not map the clock registers\n",
+ of_node_full_name(node));
+ return;
+ }
+
+ sunxi_ccu_probe(node, reg, desc);
+}
+
+static void __init sun8i_h3_r_ccu_setup(struct device_node *node)
+{
+ sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc);
+}
+CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu",
+ sun8i_h3_r_ccu_setup);
+
+static void __init sun50i_a64_r_ccu_setup(struct device_node *node)
+{
+ sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc);
+}
+CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu",
+ sun50i_a64_r_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.h b/drivers/clk/sunxi-ng/ccu-sun8i-r.h
new file mode 100644
index 000000000000..eaa431fd1d8f
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2016 Icenowy <icenowy-ymACFijhrKM@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CCU_SUN8I_R_H
+#define _CCU_SUN8I_R_H_
+
+#include <dt-bindings/clock/sun8i-r-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
+
+/* AHB/APB bus clocks are not exported */
+#define CLK_AHB0 1
+#define CLK_APB0 2
+
+#define CLK_NUMBER (CLK_APB0_TWD + 1)
+
+#endif /* _CCU_SUN8I_R_H */
diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h b/include/dt-bindings/clock/sun8i-r-ccu.h
new file mode 100644
index 000000000000..779d20aa0d05
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-r-ccu.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
+
+#define CLK_AR100 0
+
+#define CLK_APB0_PIO 3
+#define CLK_APB0_IR 4
+#define CLK_APB0_TIMER 5
+#define CLK_APB0_RSB 6
+#define CLK_APB0_UART 7
+/* 8 is reserved for CLK_APB0_W1 on A31 */
+#define CLK_APB0_I2C 9
+#define CLK_APB0_TWD 10
+
+#define CLK_IR 11
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun8i-r-ccu.h b/include/dt-bindings/reset/sun8i-r-ccu.h
new file mode 100644
index 000000000000..4ba64f3d6fc9
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-r-ccu.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_
+
+#define RST_APB0_IR 0
+#define RST_APB0_TIMER 1
+#define RST_APB0_RSB 2
+#define RST_APB0_UART 3
+/* 4 is reserved for RST_APB0_W1 on A31 */
+#define RST_APB0_I2C 5
+
+#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */
--
2.12.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 2/5] clk: sunxi-ng: add support for PRCM CCUs
@ 2017-03-15 17:28 ` Icenowy Zheng
0 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-15 17:28 UTC (permalink / raw)
To: linux-arm-kernel
SoCs after A31 has a clock controller module in the PRCM part.
Support the clock controller module on H5 and A64 now.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes in v2:
- Replace all sun6i to sun8i, as this driver currently doesn't really
support sun6i(A31).
- Add osc32000 mux for ar100 clk.
- Rename some clocks.
- Add gate of TWD (Trusted Watchdog). There's no reset for TWD.
- Removed reset of PIO, which doesn't exist really.
drivers/clk/sunxi-ng/Kconfig | 6 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-r.c | 211 ++++++++++++++++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun8i-r.h | 27 ++++
include/dt-bindings/clock/sun8i-r-ccu.h | 59 +++++++++
include/dt-bindings/reset/sun8i-r-ccu.h | 53 ++++++++
6 files changed, 357 insertions(+)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.h
create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 213cf64e4fab..056752317aee 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -150,4 +150,10 @@ config SUN9I_A80_CCU
default MACH_SUN9I
depends on MACH_SUN9I || COMPILE_TEST
+config SUN8I_R_CCU
+ bool "Support for Allwinner SoCs' PRCM CCUs"
+ select SUNXI_CCU_DIV
+ select SUNXI_CCU_GATE
+ default MACH_SUN8I || (ARCH_SUNXI && ARM64)
+
endif
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 6feaac0c5600..0ec02fe14c50 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o
+obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o
obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o
obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o
obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
new file mode 100644
index 000000000000..a6884c27c098
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun8i-r.h"
+
+static const char * const ar100_parents[] = { "osc32k", "osc24M",
+ "pll-periph0", "osc32000" };
+
+static struct ccu_div ar100_clk = {
+ .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+ .mux = {
+ .shift = 16,
+ .width = 2,
+
+ .variable_prediv = {
+ .index = 2,
+ .shift = 8,
+ .width = 5,
+ },
+ },
+
+ .common = {
+ .reg = 0x00,
+ .features = CCU_FEATURE_VARIABLE_PREDIV,
+ .hw.init = CLK_HW_INIT_PARENTS("ar100",
+ ar100_parents,
+ &ccu_div_ops,
+ 0),
+ },
+};
+
+static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0);
+
+static struct ccu_div apb0_clk = {
+ .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+ .common = {
+ .reg = 0x0c,
+ .hw.init = CLK_HW_INIT("apb0",
+ "ahb0",
+ &ccu_div_ops,
+ 0),
+ },
+};
+
+static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
+ 0x28, BIT(0), 0);
+static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0",
+ 0x28, BIT(1), 0);
+static SUNXI_CCU_GATE(apb0_timer_clk, "apb0-timer", "apb0",
+ 0x28, BIT(2), 0);
+static SUNXI_CCU_GATE(apb0_rsb_clk, "apb0-rsb", "apb0",
+ 0x28, BIT(3), 0);
+static SUNXI_CCU_GATE(apb0_uart_clk, "apb0-uart", "apb0",
+ 0x28, BIT(4), 0);
+static SUNXI_CCU_GATE(apb0_i2c_clk, "apb0-i2c", "apb0",
+ 0x28, BIT(6), 0);
+static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0",
+ 0x28, BIT(7), 0);
+
+static const char * const r_mod0_default_parents[] = { "osc32K", "osc24M" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
+ r_mod0_default_parents, 0x54,
+ 0, 4, /* M */
+ 16, 2, /* P */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static struct ccu_common *sun8i_h3_r_ccu_clks[] = {
+ &ar100_clk.common,
+ &apb0_clk.common,
+ &apb0_pio_clk.common,
+ &apb0_ir_clk.common,
+ &apb0_timer_clk.common,
+ &apb0_uart_clk.common,
+ &apb0_i2c_clk.common,
+ &ir_clk.common,
+};
+
+static struct ccu_common *sun50i_a64_r_ccu_clks[] = {
+ &ar100_clk.common,
+ &apb0_clk.common,
+ &apb0_pio_clk.common,
+ &apb0_ir_clk.common,
+ &apb0_timer_clk.common,
+ &apb0_rsb_clk.common,
+ &apb0_uart_clk.common,
+ &apb0_i2c_clk.common,
+ &ir_clk.common,
+};
+
+static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = {
+ .hws = {
+ [CLK_AR100] = &ar100_clk.common.hw,
+ [CLK_AHB0] = &ahb0_clk.hw,
+ [CLK_APB0] = &apb0_clk.common.hw,
+ [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
+ [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
+ [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
+ [CLK_APB0_UART] = &apb0_uart_clk.common.hw,
+ [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
+ [CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
+ [CLK_IR] = &ir_clk.common.hw,
+ },
+ .num = CLK_NUMBER,
+};
+
+static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = {
+ .hws = {
+ [CLK_AR100] = &ar100_clk.common.hw,
+ [CLK_AHB0] = &ahb0_clk.hw,
+ [CLK_APB0] = &apb0_clk.common.hw,
+ [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
+ [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
+ [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
+ [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw,
+ [CLK_APB0_UART] = &apb0_uart_clk.common.hw,
+ [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
+ [CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
+ [CLK_IR] = &ir_clk.common.hw,
+ },
+ .num = CLK_NUMBER,
+};
+
+static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = {
+ [RST_APB0_IR] = { 0xb0, BIT(1) },
+ [RST_APB0_TIMER] = { 0xb0, BIT(2) },
+ [RST_APB0_UART] = { 0xb0, BIT(4) },
+ [RST_APB0_I2C] = { 0xb0, BIT(6) },
+};
+
+static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = {
+ [RST_APB0_IR] = { 0xb0, BIT(1) },
+ [RST_APB0_TIMER] = { 0xb0, BIT(2) },
+ [RST_APB0_RSB] = { 0xb0, BIT(3) },
+ [RST_APB0_UART] = { 0xb0, BIT(4) },
+ [RST_APB0_I2C] = { 0xb0, BIT(6) },
+};
+
+static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = {
+ .ccu_clks = sun8i_h3_r_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks),
+
+ .hw_clks = &sun8i_h3_r_hw_clks,
+
+ .resets = sun8i_h3_r_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets),
+};
+
+static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = {
+ .ccu_clks = sun50i_a64_r_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks),
+
+ .hw_clks = &sun50i_a64_r_hw_clks,
+
+ .resets = sun50i_a64_r_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets),
+};
+
+static void __init sunxi_r_ccu_init(struct device_node *node,
+ const struct sunxi_ccu_desc *desc)
+{
+ void __iomem *reg;
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (IS_ERR(reg)) {
+ pr_err("%s: Could not map the clock registers\n",
+ of_node_full_name(node));
+ return;
+ }
+
+ sunxi_ccu_probe(node, reg, desc);
+}
+
+static void __init sun8i_h3_r_ccu_setup(struct device_node *node)
+{
+ sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc);
+}
+CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu",
+ sun8i_h3_r_ccu_setup);
+
+static void __init sun50i_a64_r_ccu_setup(struct device_node *node)
+{
+ sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc);
+}
+CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu",
+ sun50i_a64_r_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.h b/drivers/clk/sunxi-ng/ccu-sun8i-r.h
new file mode 100644
index 000000000000..eaa431fd1d8f
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2016 Icenowy <icenowy@aosc.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CCU_SUN8I_R_H
+#define _CCU_SUN8I_R_H_
+
+#include <dt-bindings/clock/sun8i-r-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
+
+/* AHB/APB bus clocks are not exported */
+#define CLK_AHB0 1
+#define CLK_APB0 2
+
+#define CLK_NUMBER (CLK_APB0_TWD + 1)
+
+#endif /* _CCU_SUN8I_R_H */
diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h b/include/dt-bindings/clock/sun8i-r-ccu.h
new file mode 100644
index 000000000000..779d20aa0d05
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-r-ccu.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
+
+#define CLK_AR100 0
+
+#define CLK_APB0_PIO 3
+#define CLK_APB0_IR 4
+#define CLK_APB0_TIMER 5
+#define CLK_APB0_RSB 6
+#define CLK_APB0_UART 7
+/* 8 is reserved for CLK_APB0_W1 on A31 */
+#define CLK_APB0_I2C 9
+#define CLK_APB0_TWD 10
+
+#define CLK_IR 11
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun8i-r-ccu.h b/include/dt-bindings/reset/sun8i-r-ccu.h
new file mode 100644
index 000000000000..4ba64f3d6fc9
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-r-ccu.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_
+
+#define RST_APB0_IR 0
+#define RST_APB0_TIMER 1
+#define RST_APB0_RSB 2
+#define RST_APB0_UART 3
+/* 4 is reserved for RST_APB0_W1 on A31 */
+#define RST_APB0_I2C 5
+
+#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */
--
2.12.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 3/5] arm64: allwinner: a64: add r_ccu node
2017-03-15 17:28 ` Icenowy Zheng
@ 2017-03-15 17:28 ` Icenowy Zheng
-1 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-15 17:28 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
A64 SoC have a CCU (r_ccu) in PRCM block.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
Changes in v2:
- Add osc32000.
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1c64ea2d23f9..dbeba43386f6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -43,8 +43,10 @@
*/
#include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
/ {
interrupt-parent = <&gic>;
@@ -98,6 +100,13 @@
clock-output-names = "osc32k";
};
+ osc32000: osc32000_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ clock-output-names = "osc32000";
+ };
+
psci {
compatible = "arm,psci-0.2";
method = "smc";
@@ -392,5 +401,14 @@
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ r_ccu: clock@1f01400 {
+ compatible = "allwinner,sun50i-a64-r-ccu";
+ reg = <0x01f01400 0x100>;
+ clocks = <&osc24M>, <&osc32k>, <&osc32000>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
};
--
2.12.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 3/5] arm64: allwinner: a64: add r_ccu node
@ 2017-03-15 17:28 ` Icenowy Zheng
0 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-15 17:28 UTC (permalink / raw)
To: linux-arm-kernel
A64 SoC have a CCU (r_ccu) in PRCM block.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes in v2:
- Add osc32000.
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1c64ea2d23f9..dbeba43386f6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -43,8 +43,10 @@
*/
#include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
/ {
interrupt-parent = <&gic>;
@@ -98,6 +100,13 @@
clock-output-names = "osc32k";
};
+ osc32000: osc32000_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ clock-output-names = "osc32000";
+ };
+
psci {
compatible = "arm,psci-0.2";
method = "smc";
@@ -392,5 +401,14 @@
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ r_ccu: clock at 1f01400 {
+ compatible = "allwinner,sun50i-a64-r-ccu";
+ reg = <0x01f01400 0x100>;
+ clocks = <&osc24M>, <&osc32k>, <&osc32000>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
};
--
2.12.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 4/5] ARM: sun8i: h3: switch apb0-related clocks to r_ccu
2017-03-15 17:28 ` Icenowy Zheng
@ 2017-03-15 17:28 ` Icenowy Zheng
-1 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-15 17:28 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
Now we have driver for the PRCM CCU, switch to use it instead of
old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi .
Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
New patch in v2.
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 46 +++++++++++++-------------------------
1 file changed, 15 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 2494ea063cd4..710e429a3d03 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -41,8 +41,10 @@
*/
#include <dt-bindings/clock/sun8i-h3-ccu.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
/ {
interrupt-parent = <&gic>;
@@ -68,31 +70,11 @@
clock-output-names = "osc32k";
};
- apb0: apb0_clk {
- compatible = "fixed-factor-clock";
+ osc32000: osc32000_clk {
#clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&osc24M>;
- clock-output-names = "apb0";
- };
-
- apb0_gates: clk@01f01428 {
- compatible = "allwinner,sun8i-h3-apb0-gates-clk",
- "allwinner,sun4i-a10-gates-clk";
- reg = <0x01f01428 0x4>;
- #clock-cells = <1>;
- clocks = <&apb0>;
- clock-indices = <0>, <1>;
- clock-output-names = "apb0_pio", "apb0_ir";
- };
-
- ir_clk: ir_clk@01f01454 {
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01f01454 0x4>;
- #clock-cells = <0>;
- clocks = <&osc32k>, <&osc24M>;
- clock-output-names = "ir";
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ clock-output-names = "osc32000";
};
};
@@ -544,9 +526,12 @@
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
- apb0_reset: reset@01f014b0 {
- reg = <0x01f014b0 0x4>;
- compatible = "allwinner,sun6i-a31-clock-reset";
+ r_ccu: clock@1f01400 {
+ compatible = "allwinner,sun50i-a64-r-ccu";
+ reg = <0x01f01400 0x100>;
+ clocks = <&osc24M>, <&osc32k>, <&osc32000>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
#reset-cells = <1>;
};
@@ -557,9 +542,9 @@
ir: ir@01f02000 {
compatible = "allwinner,sun5i-a13-ir";
- clocks = <&apb0_gates 1>, <&ir_clk>;
+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
clock-names = "apb", "ir";
- resets = <&apb0_reset 1>;
+ resets = <&r_ccu RST_APB0_IR>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x01f02000 0x40>;
status = "disabled";
@@ -569,9 +554,8 @@
compatible = "allwinner,sun8i-h3-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
+ clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
- resets = <&apb0_reset 0>;
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
--
2.12.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 4/5] ARM: sun8i: h3: switch apb0-related clocks to r_ccu
@ 2017-03-15 17:28 ` Icenowy Zheng
0 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-15 17:28 UTC (permalink / raw)
To: linux-arm-kernel
Now we have driver for the PRCM CCU, switch to use it instead of
old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi .
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
New patch in v2.
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 46 +++++++++++++-------------------------
1 file changed, 15 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 2494ea063cd4..710e429a3d03 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -41,8 +41,10 @@
*/
#include <dt-bindings/clock/sun8i-h3-ccu.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
/ {
interrupt-parent = <&gic>;
@@ -68,31 +70,11 @@
clock-output-names = "osc32k";
};
- apb0: apb0_clk {
- compatible = "fixed-factor-clock";
+ osc32000: osc32000_clk {
#clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&osc24M>;
- clock-output-names = "apb0";
- };
-
- apb0_gates: clk at 01f01428 {
- compatible = "allwinner,sun8i-h3-apb0-gates-clk",
- "allwinner,sun4i-a10-gates-clk";
- reg = <0x01f01428 0x4>;
- #clock-cells = <1>;
- clocks = <&apb0>;
- clock-indices = <0>, <1>;
- clock-output-names = "apb0_pio", "apb0_ir";
- };
-
- ir_clk: ir_clk at 01f01454 {
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01f01454 0x4>;
- #clock-cells = <0>;
- clocks = <&osc32k>, <&osc24M>;
- clock-output-names = "ir";
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ clock-output-names = "osc32000";
};
};
@@ -544,9 +526,12 @@
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
- apb0_reset: reset at 01f014b0 {
- reg = <0x01f014b0 0x4>;
- compatible = "allwinner,sun6i-a31-clock-reset";
+ r_ccu: clock at 1f01400 {
+ compatible = "allwinner,sun50i-a64-r-ccu";
+ reg = <0x01f01400 0x100>;
+ clocks = <&osc24M>, <&osc32k>, <&osc32000>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
#reset-cells = <1>;
};
@@ -557,9 +542,9 @@
ir: ir at 01f02000 {
compatible = "allwinner,sun5i-a13-ir";
- clocks = <&apb0_gates 1>, <&ir_clk>;
+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
clock-names = "apb", "ir";
- resets = <&apb0_reset 1>;
+ resets = <&r_ccu RST_APB0_IR>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x01f02000 0x40>;
status = "disabled";
@@ -569,9 +554,8 @@
compatible = "allwinner,sun8i-h3-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
+ clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
- resets = <&apb0_reset 0>;
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
--
2.12.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 5/5] arm64: allwinner: a64: add R_PIO pinctrl node
2017-03-15 17:28 ` Icenowy Zheng
@ 2017-03-15 17:28 ` Icenowy Zheng
-1 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-15 17:28 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
Allwinner A64 have a dedicated pin controller to manage the PL pin bank.
As the driver and the required clock support are added, add the device
node for it.
Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
New patch in v2.
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index dbeba43386f6..a59fec6f2a22 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -410,5 +410,17 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ r_pio: pinctrl@01f02c00 {
+ compatible = "allwinner,sun50i-a64-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
};
};
--
2.12.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 5/5] arm64: allwinner: a64: add R_PIO pinctrl node
@ 2017-03-15 17:28 ` Icenowy Zheng
0 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-15 17:28 UTC (permalink / raw)
To: linux-arm-kernel
Allwinner A64 have a dedicated pin controller to manage the PL pin bank.
As the driver and the required clock support are added, add the device
node for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
New patch in v2.
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index dbeba43386f6..a59fec6f2a22 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -410,5 +410,17 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ r_pio: pinctrl at 01f02c00 {
+ compatible = "allwinner,sun50i-a64-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
};
};
--
2.12.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
@ 2017-03-21 7:41 ` Maxime Ripard
0 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2017-03-21 7:41 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Chen-Yu Tsai, devicetree, linux-arm-kernel,
linux-kernel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 2146 bytes --]
On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
> Many Allwinner SoCs after A31 have a CCU in PRCM block.
>
> Give the ones on H3 and A64 compatible strings.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> Changes in v2:
> - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
> clock for mux 3 of ar100 clk. Investgations are needed for them.)
>
> Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> index 68512aa398a9..4a4addff595d 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> @@ -7,9 +7,11 @@ Required properties :
> - "allwinner,sun8i-a23-ccu"
> - "allwinner,sun8i-a33-ccu"
> - "allwinner,sun8i-h3-ccu"
> + - "allwinner,sun8i-h3-r-ccu"
> - "allwinner,sun8i-v3s-ccu"
> - "allwinner,sun9i-a80-ccu"
> - "allwinner,sun50i-a64-ccu"
> + - "allwinner,sun50i-a64-r-ccu"
> - "allwinner,sun50i-h5-ccu"
>
> - reg: Must contain the registers base address and length
> @@ -20,7 +22,11 @@ Required properties :
> - #clock-cells : must contain 1
> - #reset-cells : must contain 1
>
> -Example:
> +For the PRCM CCUs on H3/A64, one more clock is needed:
> +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
> + not the same with losc)
This is called the internal oscillator in the datasheet, it would
probably make more sense to call it that way in the documentation too.
This oscillator seems to be clocked at 16MHz, so we should represent
it as such.
And I'm wondering, are you *sure* that it's fed directly from the
internal oscillator, or goes through the registers in the RTC, with
the 32 divider and 16 prescaler by default that makes it at roughly
the same rate (31.25kHz).
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
@ 2017-03-21 7:41 ` Maxime Ripard
0 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2017-03-21 7:41 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Chen-Yu Tsai, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
[-- Attachment #1: Type: text/plain, Size: 2109 bytes --]
On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
> Many Allwinner SoCs after A31 have a CCU in PRCM block.
>
> Give the ones on H3 and A64 compatible strings.
>
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> ---
> Changes in v2:
> - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
> clock for mux 3 of ar100 clk. Investgations are needed for them.)
>
> Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> index 68512aa398a9..4a4addff595d 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> @@ -7,9 +7,11 @@ Required properties :
> - "allwinner,sun8i-a23-ccu"
> - "allwinner,sun8i-a33-ccu"
> - "allwinner,sun8i-h3-ccu"
> + - "allwinner,sun8i-h3-r-ccu"
> - "allwinner,sun8i-v3s-ccu"
> - "allwinner,sun9i-a80-ccu"
> - "allwinner,sun50i-a64-ccu"
> + - "allwinner,sun50i-a64-r-ccu"
> - "allwinner,sun50i-h5-ccu"
>
> - reg: Must contain the registers base address and length
> @@ -20,7 +22,11 @@ Required properties :
> - #clock-cells : must contain 1
> - #reset-cells : must contain 1
>
> -Example:
> +For the PRCM CCUs on H3/A64, one more clock is needed:
> +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
> + not the same with losc)
This is called the internal oscillator in the datasheet, it would
probably make more sense to call it that way in the documentation too.
This oscillator seems to be clocked at 16MHz, so we should represent
it as such.
And I'm wondering, are you *sure* that it's fed directly from the
internal oscillator, or goes through the registers in the RTC, with
the 32 divider and 16 prescaler by default that makes it at roughly
the same rate (31.25kHz).
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
@ 2017-03-21 7:41 ` Maxime Ripard
0 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2017-03-21 7:41 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
> Many Allwinner SoCs after A31 have a CCU in PRCM block.
>
> Give the ones on H3 and A64 compatible strings.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> Changes in v2:
> - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
> clock for mux 3 of ar100 clk. Investgations are needed for them.)
>
> Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> index 68512aa398a9..4a4addff595d 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> @@ -7,9 +7,11 @@ Required properties :
> - "allwinner,sun8i-a23-ccu"
> - "allwinner,sun8i-a33-ccu"
> - "allwinner,sun8i-h3-ccu"
> + - "allwinner,sun8i-h3-r-ccu"
> - "allwinner,sun8i-v3s-ccu"
> - "allwinner,sun9i-a80-ccu"
> - "allwinner,sun50i-a64-ccu"
> + - "allwinner,sun50i-a64-r-ccu"
> - "allwinner,sun50i-h5-ccu"
>
> - reg: Must contain the registers base address and length
> @@ -20,7 +22,11 @@ Required properties :
> - #clock-cells : must contain 1
> - #reset-cells : must contain 1
>
> -Example:
> +For the PRCM CCUs on H3/A64, one more clock is needed:
> +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
> + not the same with losc)
This is called the internal oscillator in the datasheet, it would
probably make more sense to call it that way in the documentation too.
This oscillator seems to be clocked at 16MHz, so we should represent
it as such.
And I'm wondering, are you *sure* that it's fed directly from the
internal oscillator, or goes through the registers in the RTC, with
the 32 divider and 16 prescaler by default that makes it at roughly
the same rate (31.25kHz).
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
2017-03-21 7:41 ` Maxime Ripard
@ 2017-03-21 18:22 ` Icenowy Zheng
-1 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-21 18:22 UTC (permalink / raw)
To: Maxime Ripard
Cc: Rob Herring, Chen-Yu Tsai, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
21.03.2017, 15:41, "Maxime Ripard" <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>:
> On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
>> Many Allwinner SoCs after A31 have a CCU in PRCM block.
>>
>> Give the ones on H3 and A64 compatible strings.
>>
>> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>> ---
>> Changes in v2:
>> - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
>> clock for mux 3 of ar100 clk. Investgations are needed for them.)
>>
>> Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
>> 1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
>> index 68512aa398a9..4a4addff595d 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
>> @@ -7,9 +7,11 @@ Required properties :
>> - "allwinner,sun8i-a23-ccu"
>> - "allwinner,sun8i-a33-ccu"
>> - "allwinner,sun8i-h3-ccu"
>> + - "allwinner,sun8i-h3-r-ccu"
>> - "allwinner,sun8i-v3s-ccu"
>> - "allwinner,sun9i-a80-ccu"
>> - "allwinner,sun50i-a64-ccu"
>> + - "allwinner,sun50i-a64-r-ccu"
>> - "allwinner,sun50i-h5-ccu"
>>
>> - reg: Must contain the registers base address and length
>> @@ -20,7 +22,11 @@ Required properties :
>> - #clock-cells : must contain 1
>> - #reset-cells : must contain 1
>>
>> -Example:
>> +For the PRCM CCUs on H3/A64, one more clock is needed:
>> +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
>> + not the same with losc)
>
> This is called the internal oscillator in the datasheet, it would
> probably make more sense to call it that way in the documentation too.
>
> This oscillator seems to be clocked at 16MHz, so we should represent
> it as such.
>
> And I'm wondering, are you *sure* that it's fed directly from the
> internal oscillator, or goes through the registers in the RTC, with
> the 32 divider and 16 prescaler by default that makes it at roughly
> the same rate (31.25kHz).
In fact I know nothing about it -- I only represented the code in BSP
clock driver.
The mux value 3 varies from SoC to SoC. For A64/H5 it's 32000,
for A33 it's 667000 (seems to be directly the internal OSC, as the
user manual says the internal OSC is 600~700kHz; but it's named
cpuosc rather than iosc in A33 BSP clock driver); for A80 it's even
PLL_AUDIO.
Maybe we should find a way to deal with it before it's finally revealed?
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
--
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To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
@ 2017-03-21 18:22 ` Icenowy Zheng
0 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-21 18:22 UTC (permalink / raw)
To: linux-arm-kernel
21.03.2017, 15:41, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
>> ?Many Allwinner SoCs after A31 have a CCU in PRCM block.
>>
>> ?Give the ones on H3 and A64 compatible strings.
>>
>> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>> ?---
>> ?Changes in v2:
>> ?- Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
>> ???clock for mux 3 of ar100 clk. Investgations are needed for them.)
>>
>> ??Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
>> ??1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> ?diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
>> ?index 68512aa398a9..4a4addff595d 100644
>> ?--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
>> ?+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
>> ?@@ -7,9 +7,11 @@ Required properties :
>> ??????????????????- "allwinner,sun8i-a23-ccu"
>> ??????????????????- "allwinner,sun8i-a33-ccu"
>> ??????????????????- "allwinner,sun8i-h3-ccu"
>> ?+ - "allwinner,sun8i-h3-r-ccu"
>> ??????????????????- "allwinner,sun8i-v3s-ccu"
>> ??????????????????- "allwinner,sun9i-a80-ccu"
>> ??????????????????- "allwinner,sun50i-a64-ccu"
>> ?+ - "allwinner,sun50i-a64-r-ccu"
>> ??????????????????- "allwinner,sun50i-h5-ccu"
>>
>> ??- reg: Must contain the registers base address and length
>> ?@@ -20,7 +22,11 @@ Required properties :
>> ??- #clock-cells : must contain 1
>> ??- #reset-cells : must contain 1
>>
>> ?-Example:
>> ?+For the PRCM CCUs on H3/A64, one more clock is needed:
>> ?+- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
>> ?+ not the same with losc)
>
> This is called the internal oscillator in the datasheet, it would
> probably make more sense to call it that way in the documentation too.
>
> This oscillator seems to be clocked at 16MHz, so we should represent
> it as such.
>
> And I'm wondering, are you *sure* that it's fed directly from the
> internal oscillator, or goes through the registers in the RTC, with
> the 32 divider and 16 prescaler by default that makes it at roughly
> the same rate (31.25kHz).
In fact I know nothing about it -- I only represented the code in BSP
clock driver.
The mux value 3 varies from SoC to SoC. For A64/H5 it's 32000,
for A33 it's 667000 (seems to be directly the internal OSC, as the
user manual says the internal OSC is 600~700kHz; but it's named
cpuosc rather than iosc in A33 BSP clock driver); for A80 it's even
PLL_AUDIO.
Maybe we should find a way to deal with it before it's finally revealed?
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
@ 2017-03-22 20:09 ` Maxime Ripard
0 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2017-03-22 20:09 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Chen-Yu Tsai, devicetree, linux-arm-kernel,
linux-kernel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 3824 bytes --]
On Wed, Mar 22, 2017 at 02:22:22AM +0800, Icenowy Zheng wrote:
>
>
> 21.03.2017, 15:41, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> > On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
> >> Many Allwinner SoCs after A31 have a CCU in PRCM block.
> >>
> >> Give the ones on H3 and A64 compatible strings.
> >>
> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >> ---
> >> Changes in v2:
> >> - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
> >> clock for mux 3 of ar100 clk. Investgations are needed for them.)
> >>
> >> Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
> >> 1 file changed, 17 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> index 68512aa398a9..4a4addff595d 100644
> >> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> @@ -7,9 +7,11 @@ Required properties :
> >> - "allwinner,sun8i-a23-ccu"
> >> - "allwinner,sun8i-a33-ccu"
> >> - "allwinner,sun8i-h3-ccu"
> >> + - "allwinner,sun8i-h3-r-ccu"
> >> - "allwinner,sun8i-v3s-ccu"
> >> - "allwinner,sun9i-a80-ccu"
> >> - "allwinner,sun50i-a64-ccu"
> >> + - "allwinner,sun50i-a64-r-ccu"
> >> - "allwinner,sun50i-h5-ccu"
> >>
> >> - reg: Must contain the registers base address and length
> >> @@ -20,7 +22,11 @@ Required properties :
> >> - #clock-cells : must contain 1
> >> - #reset-cells : must contain 1
> >>
> >> -Example:
> >> +For the PRCM CCUs on H3/A64, one more clock is needed:
> >> +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
> >> + not the same with losc)
> >
> > This is called the internal oscillator in the datasheet, it would
> > probably make more sense to call it that way in the documentation too.
> >
> > This oscillator seems to be clocked at 16MHz, so we should represent
> > it as such.
> >
> > And I'm wondering, are you *sure* that it's fed directly from the
> > internal oscillator, or goes through the registers in the RTC, with
> > the 32 divider and 16 prescaler by default that makes it at roughly
> > the same rate (31.25kHz).
>
> In fact I know nothing about it -- I only represented the code in BSP
> clock driver.
>
> The mux value 3 varies from SoC to SoC. For A64/H5 it's 32000,
> for A33 it's 667000 (seems to be directly the internal OSC, as the
> user manual says the internal OSC is 600~700kHz; but it's named
> cpuosc rather than iosc in A33 BSP clock driver); for A80 it's even
> PLL_AUDIO.
Where are you getting those info from?
As far as I know, the A33 PRCM takes the hosc, losc, pll6 and CPU
(internal) oscillator:
https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L508
The H3 takes the hosc and losc:
https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw7.c#L379
The A80 takes the hosc and losc:
https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun9iw1.c#L281
The A64 takes the hosc, losc, pll-periph0 and the iosc, which indeed
seems to be fed from the internal oscillator with the divider in the
RTC:
https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/arch/arm64/boot/dts/sun50iw1p1-clk.dtsi#L19
https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/drivers/clk/sunxi/clk-sun50iw1.c#L603
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
@ 2017-03-22 20:09 ` Maxime Ripard
0 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2017-03-22 20:09 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Chen-Yu Tsai, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
[-- Attachment #1: Type: text/plain, Size: 4354 bytes --]
On Wed, Mar 22, 2017 at 02:22:22AM +0800, Icenowy Zheng wrote:
>
>
> 21.03.2017, 15:41, "Maxime Ripard" <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>:
> > On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
> >> Many Allwinner SoCs after A31 have a CCU in PRCM block.
> >>
> >> Give the ones on H3 and A64 compatible strings.
> >>
> >> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> >> ---
> >> Changes in v2:
> >> - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
> >> clock for mux 3 of ar100 clk. Investgations are needed for them.)
> >>
> >> Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
> >> 1 file changed, 17 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> index 68512aa398a9..4a4addff595d 100644
> >> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> @@ -7,9 +7,11 @@ Required properties :
> >> - "allwinner,sun8i-a23-ccu"
> >> - "allwinner,sun8i-a33-ccu"
> >> - "allwinner,sun8i-h3-ccu"
> >> + - "allwinner,sun8i-h3-r-ccu"
> >> - "allwinner,sun8i-v3s-ccu"
> >> - "allwinner,sun9i-a80-ccu"
> >> - "allwinner,sun50i-a64-ccu"
> >> + - "allwinner,sun50i-a64-r-ccu"
> >> - "allwinner,sun50i-h5-ccu"
> >>
> >> - reg: Must contain the registers base address and length
> >> @@ -20,7 +22,11 @@ Required properties :
> >> - #clock-cells : must contain 1
> >> - #reset-cells : must contain 1
> >>
> >> -Example:
> >> +For the PRCM CCUs on H3/A64, one more clock is needed:
> >> +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
> >> + not the same with losc)
> >
> > This is called the internal oscillator in the datasheet, it would
> > probably make more sense to call it that way in the documentation too.
> >
> > This oscillator seems to be clocked at 16MHz, so we should represent
> > it as such.
> >
> > And I'm wondering, are you *sure* that it's fed directly from the
> > internal oscillator, or goes through the registers in the RTC, with
> > the 32 divider and 16 prescaler by default that makes it at roughly
> > the same rate (31.25kHz).
>
> In fact I know nothing about it -- I only represented the code in BSP
> clock driver.
>
> The mux value 3 varies from SoC to SoC. For A64/H5 it's 32000,
> for A33 it's 667000 (seems to be directly the internal OSC, as the
> user manual says the internal OSC is 600~700kHz; but it's named
> cpuosc rather than iosc in A33 BSP clock driver); for A80 it's even
> PLL_AUDIO.
Where are you getting those info from?
As far as I know, the A33 PRCM takes the hosc, losc, pll6 and CPU
(internal) oscillator:
https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L508
The H3 takes the hosc and losc:
https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw7.c#L379
The A80 takes the hosc and losc:
https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun9iw1.c#L281
The A64 takes the hosc, losc, pll-periph0 and the iosc, which indeed
seems to be fed from the internal oscillator with the divider in the
RTC:
https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/arch/arm64/boot/dts/sun50iw1p1-clk.dtsi#L19
https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/drivers/clk/sunxi/clk-sun50iw1.c#L603
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
--
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
@ 2017-03-22 20:09 ` Maxime Ripard
0 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2017-03-22 20:09 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Mar 22, 2017 at 02:22:22AM +0800, Icenowy Zheng wrote:
>
>
> 21.03.2017, 15:41, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> > On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
> >> ?Many Allwinner SoCs after A31 have a CCU in PRCM block.
> >>
> >> ?Give the ones on H3 and A64 compatible strings.
> >>
> >> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >> ?---
> >> ?Changes in v2:
> >> ?- Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
> >> ???clock for mux 3 of ar100 clk. Investgations are needed for them.)
> >>
> >> ??Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
> >> ??1 file changed, 17 insertions(+), 1 deletion(-)
> >>
> >> ?diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> ?index 68512aa398a9..4a4addff595d 100644
> >> ?--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> ?+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> ?@@ -7,9 +7,11 @@ Required properties :
> >> ??????????????????- "allwinner,sun8i-a23-ccu"
> >> ??????????????????- "allwinner,sun8i-a33-ccu"
> >> ??????????????????- "allwinner,sun8i-h3-ccu"
> >> ?+ - "allwinner,sun8i-h3-r-ccu"
> >> ??????????????????- "allwinner,sun8i-v3s-ccu"
> >> ??????????????????- "allwinner,sun9i-a80-ccu"
> >> ??????????????????- "allwinner,sun50i-a64-ccu"
> >> ?+ - "allwinner,sun50i-a64-r-ccu"
> >> ??????????????????- "allwinner,sun50i-h5-ccu"
> >>
> >> ??- reg: Must contain the registers base address and length
> >> ?@@ -20,7 +22,11 @@ Required properties :
> >> ??- #clock-cells : must contain 1
> >> ??- #reset-cells : must contain 1
> >>
> >> ?-Example:
> >> ?+For the PRCM CCUs on H3/A64, one more clock is needed:
> >> ?+- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
> >> ?+ not the same with losc)
> >
> > This is called the internal oscillator in the datasheet, it would
> > probably make more sense to call it that way in the documentation too.
> >
> > This oscillator seems to be clocked at 16MHz, so we should represent
> > it as such.
> >
> > And I'm wondering, are you *sure* that it's fed directly from the
> > internal oscillator, or goes through the registers in the RTC, with
> > the 32 divider and 16 prescaler by default that makes it at roughly
> > the same rate (31.25kHz).
>
> In fact I know nothing about it -- I only represented the code in BSP
> clock driver.
>
> The mux value 3 varies from SoC to SoC. For A64/H5 it's 32000,
> for A33 it's 667000 (seems to be directly the internal OSC, as the
> user manual says the internal OSC is 600~700kHz; but it's named
> cpuosc rather than iosc in A33 BSP clock driver); for A80 it's even
> PLL_AUDIO.
Where are you getting those info from?
As far as I know, the A33 PRCM takes the hosc, losc, pll6 and CPU
(internal) oscillator:
https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L508
The H3 takes the hosc and losc:
https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw7.c#L379
The A80 takes the hosc and losc:
https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun9iw1.c#L281
The A64 takes the hosc, losc, pll-periph0 and the iosc, which indeed
seems to be fed from the internal oscillator with the divider in the
RTC:
https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/arch/arm64/boot/dts/sun50iw1p1-clk.dtsi#L19
https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/drivers/clk/sunxi/clk-sun50iw1.c#L603
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
2017-03-22 20:09 ` Maxime Ripard
@ 2017-03-22 23:17 ` Icenowy Zheng
-1 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-22 23:17 UTC (permalink / raw)
To: Maxime Ripard
Cc: Rob Herring, Chen-Yu Tsai, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
23.03.2017, 04:09, "Maxime Ripard" <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>:
> On Wed, Mar 22, 2017 at 02:22:22AM +0800, Icenowy Zheng wrote:
>> 21.03.2017, 15:41, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
>> > On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
>> >> Many Allwinner SoCs after A31 have a CCU in PRCM block.
>> >>
>> >> Give the ones on H3 and A64 compatible strings.
>> >>
>> >> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>> >> ---
>> >> Changes in v2:
>> >> - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
>> >> clock for mux 3 of ar100 clk. Investgations are needed for them.)
>> >>
>> >> Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
>> >> 1 file changed, 17 insertions(+), 1 deletion(-)
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
>> >> index 68512aa398a9..4a4addff595d 100644
>> >> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
>> >> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
>> >> @@ -7,9 +7,11 @@ Required properties :
>> >> - "allwinner,sun8i-a23-ccu"
>> >> - "allwinner,sun8i-a33-ccu"
>> >> - "allwinner,sun8i-h3-ccu"
>> >> + - "allwinner,sun8i-h3-r-ccu"
>> >> - "allwinner,sun8i-v3s-ccu"
>> >> - "allwinner,sun9i-a80-ccu"
>> >> - "allwinner,sun50i-a64-ccu"
>> >> + - "allwinner,sun50i-a64-r-ccu"
>> >> - "allwinner,sun50i-h5-ccu"
>> >>
>> >> - reg: Must contain the registers base address and length
>> >> @@ -20,7 +22,11 @@ Required properties :
>> >> - #clock-cells : must contain 1
>> >> - #reset-cells : must contain 1
>> >>
>> >> -Example:
>> >> +For the PRCM CCUs on H3/A64, one more clock is needed:
>> >> +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
>> >> + not the same with losc)
>> >
>> > This is called the internal oscillator in the datasheet, it would
>> > probably make more sense to call it that way in the documentation too.
>> >
>> > This oscillator seems to be clocked at 16MHz, so we should represent
>> > it as such.
>> >
>> > And I'm wondering, are you *sure* that it's fed directly from the
>> > internal oscillator, or goes through the registers in the RTC, with
>> > the 32 divider and 16 prescaler by default that makes it at roughly
>> > the same rate (31.25kHz).
>>
>> In fact I know nothing about it -- I only represented the code in BSP
>> clock driver.
>>
>> The mux value 3 varies from SoC to SoC. For A64/H5 it's 32000,
>> for A33 it's 667000 (seems to be directly the internal OSC, as the
>> user manual says the internal OSC is 600~700kHz; but it's named
>> cpuosc rather than iosc in A33 BSP clock driver); for A80 it's even
>> PLL_AUDIO.
>
> Where are you getting those info from?
>
> As far as I know, the A33 PRCM takes the hosc, losc, pll6 and CPU
> (internal) oscillator:
> https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L508
>
> The H3 takes the hosc and losc:
> https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw7.c#L379
>
> The A80 takes the hosc and losc:
> https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun9iw1.c#L281
>
> The A64 takes the hosc, losc, pll-periph0 and the iosc, which indeed
> seems to be fed from the internal oscillator with the divider in the
> RTC:
> https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/arch/arm64/boot/dts/sun50iw1p1-clk.dtsi#L19
> https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/drivers/clk/sunxi/clk-sun50iw1.c#L603
But then in sunxi_init_clocks function, the iosc clock is initialized
as a fixed clock with 32000Hz.
The clock node in BSP device tree have a compatible of
allwinner,fixed-clock, but not fixed-clock, which makes it not able
to be really probed.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
--
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
@ 2017-03-22 23:17 ` Icenowy Zheng
0 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2017-03-22 23:17 UTC (permalink / raw)
To: linux-arm-kernel
23.03.2017, 04:09, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> On Wed, Mar 22, 2017 at 02:22:22AM +0800, Icenowy Zheng wrote:
>> ?21.03.2017, 15:41, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
>> ?> On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
>> ?>> ?Many Allwinner SoCs after A31 have a CCU in PRCM block.
>> ?>>
>> ?>> ?Give the ones on H3 and A64 compatible strings.
>> ?>>
>> ?>> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>> ?>> ?---
>> ?>> ?Changes in v2:
>> ?>> ?- Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
>> ?>> ???clock for mux 3 of ar100 clk. Investgations are needed for them.)
>> ?>>
>> ?>> ??Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
>> ?>> ??1 file changed, 17 insertions(+), 1 deletion(-)
>> ?>>
>> ?>> ?diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
>> ?>> ?index 68512aa398a9..4a4addff595d 100644
>> ?>> ?--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
>> ?>> ?+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
>> ?>> ?@@ -7,9 +7,11 @@ Required properties :
>> ?>> ??????????????????- "allwinner,sun8i-a23-ccu"
>> ?>> ??????????????????- "allwinner,sun8i-a33-ccu"
>> ?>> ??????????????????- "allwinner,sun8i-h3-ccu"
>> ?>> ?+ - "allwinner,sun8i-h3-r-ccu"
>> ?>> ??????????????????- "allwinner,sun8i-v3s-ccu"
>> ?>> ??????????????????- "allwinner,sun9i-a80-ccu"
>> ?>> ??????????????????- "allwinner,sun50i-a64-ccu"
>> ?>> ?+ - "allwinner,sun50i-a64-r-ccu"
>> ?>> ??????????????????- "allwinner,sun50i-h5-ccu"
>> ?>>
>> ?>> ??- reg: Must contain the registers base address and length
>> ?>> ?@@ -20,7 +22,11 @@ Required properties :
>> ?>> ??- #clock-cells : must contain 1
>> ?>> ??- #reset-cells : must contain 1
>> ?>>
>> ?>> ?-Example:
>> ?>> ?+For the PRCM CCUs on H3/A64, one more clock is needed:
>> ?>> ?+- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
>> ?>> ?+ not the same with losc)
>> ?>
>> ?> This is called the internal oscillator in the datasheet, it would
>> ?> probably make more sense to call it that way in the documentation too.
>> ?>
>> ?> This oscillator seems to be clocked at 16MHz, so we should represent
>> ?> it as such.
>> ?>
>> ?> And I'm wondering, are you *sure* that it's fed directly from the
>> ?> internal oscillator, or goes through the registers in the RTC, with
>> ?> the 32 divider and 16 prescaler by default that makes it at roughly
>> ?> the same rate (31.25kHz).
>>
>> ?In fact I know nothing about it -- I only represented the code in BSP
>> ?clock driver.
>>
>> ?The mux value 3 varies from SoC to SoC. For A64/H5 it's 32000,
>> ?for A33 it's 667000 (seems to be directly the internal OSC, as the
>> ?user manual says the internal OSC is 600~700kHz; but it's named
>> ?cpuosc rather than iosc in A33 BSP clock driver); for A80 it's even
>> ?PLL_AUDIO.
>
> Where are you getting those info from?
>
> As far as I know, the A33 PRCM takes the hosc, losc, pll6 and CPU
> (internal) oscillator:
> https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L508
>
> The H3 takes the hosc and losc:
> https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw7.c#L379
>
> The A80 takes the hosc and losc:
> https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun9iw1.c#L281
>
> The A64 takes the hosc, losc, pll-periph0 and the iosc, which indeed
> seems to be fed from the internal oscillator with the divider in the
> RTC:
> https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/arch/arm64/boot/dts/sun50iw1p1-clk.dtsi#L19
> https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/drivers/clk/sunxi/clk-sun50iw1.c#L603
But then in sunxi_init_clocks function, the iosc clock is initialized
as a fixed clock with 32000Hz.
The clock node in BSP device tree have a compatible of
allwinner,fixed-clock, but not fixed-clock, which makes it not able
to be really probed.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
@ 2017-03-26 13:10 ` Maxime Ripard
0 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2017-03-26 13:10 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Chen-Yu Tsai, devicetree, linux-arm-kernel,
linux-kernel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 4676 bytes --]
On Thu, Mar 23, 2017 at 07:17:03AM +0800, Icenowy Zheng wrote:
>
>
> 23.03.2017, 04:09, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> > On Wed, Mar 22, 2017 at 02:22:22AM +0800, Icenowy Zheng wrote:
> >> 21.03.2017, 15:41, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> >> > On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
> >> >> Many Allwinner SoCs after A31 have a CCU in PRCM block.
> >> >>
> >> >> Give the ones on H3 and A64 compatible strings.
> >> >>
> >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >> >> ---
> >> >> Changes in v2:
> >> >> - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
> >> >> clock for mux 3 of ar100 clk. Investgations are needed for them.)
> >> >>
> >> >> Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
> >> >> 1 file changed, 17 insertions(+), 1 deletion(-)
> >> >>
> >> >> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> >> index 68512aa398a9..4a4addff595d 100644
> >> >> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> >> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> >> @@ -7,9 +7,11 @@ Required properties :
> >> >> - "allwinner,sun8i-a23-ccu"
> >> >> - "allwinner,sun8i-a33-ccu"
> >> >> - "allwinner,sun8i-h3-ccu"
> >> >> + - "allwinner,sun8i-h3-r-ccu"
> >> >> - "allwinner,sun8i-v3s-ccu"
> >> >> - "allwinner,sun9i-a80-ccu"
> >> >> - "allwinner,sun50i-a64-ccu"
> >> >> + - "allwinner,sun50i-a64-r-ccu"
> >> >> - "allwinner,sun50i-h5-ccu"
> >> >>
> >> >> - reg: Must contain the registers base address and length
> >> >> @@ -20,7 +22,11 @@ Required properties :
> >> >> - #clock-cells : must contain 1
> >> >> - #reset-cells : must contain 1
> >> >>
> >> >> -Example:
> >> >> +For the PRCM CCUs on H3/A64, one more clock is needed:
> >> >> +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
> >> >> + not the same with losc)
> >> >
> >> > This is called the internal oscillator in the datasheet, it would
> >> > probably make more sense to call it that way in the documentation too.
> >> >
> >> > This oscillator seems to be clocked at 16MHz, so we should represent
> >> > it as such.
> >> >
> >> > And I'm wondering, are you *sure* that it's fed directly from the
> >> > internal oscillator, or goes through the registers in the RTC, with
> >> > the 32 divider and 16 prescaler by default that makes it at roughly
> >> > the same rate (31.25kHz).
> >>
> >> In fact I know nothing about it -- I only represented the code in BSP
> >> clock driver.
> >>
> >> The mux value 3 varies from SoC to SoC. For A64/H5 it's 32000,
> >> for A33 it's 667000 (seems to be directly the internal OSC, as the
> >> user manual says the internal OSC is 600~700kHz; but it's named
> >> cpuosc rather than iosc in A33 BSP clock driver); for A80 it's even
> >> PLL_AUDIO.
> >
> > Where are you getting those info from?
> >
> > As far as I know, the A33 PRCM takes the hosc, losc, pll6 and CPU
> > (internal) oscillator:
> > https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L508
> >
> > The H3 takes the hosc and losc:
> > https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw7.c#L379
> >
> > The A80 takes the hosc and losc:
> > https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun9iw1.c#L281
> >
> > The A64 takes the hosc, losc, pll-periph0 and the iosc, which indeed
> > seems to be fed from the internal oscillator with the divider in the
> > RTC:
> > https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/arch/arm64/boot/dts/sun50iw1p1-clk.dtsi#L19
> > https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/drivers/clk/sunxi/clk-sun50iw1.c#L603
>
> But then in sunxi_init_clocks function, the iosc clock is initialized
> as a fixed clock with 32000Hz.
>
> The clock node in BSP device tree have a compatible of
> allwinner,fixed-clock, but not fixed-clock, which makes it not able
> to be really probed.
That clock is registered:
https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/drivers/clk/sunxi/clk-sun50iw1.c#L1193
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
@ 2017-03-26 13:10 ` Maxime Ripard
0 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2017-03-26 13:10 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Chen-Yu Tsai, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
[-- Attachment #1: Type: text/plain, Size: 5263 bytes --]
On Thu, Mar 23, 2017 at 07:17:03AM +0800, Icenowy Zheng wrote:
>
>
> 23.03.2017, 04:09, "Maxime Ripard" <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>:
> > On Wed, Mar 22, 2017 at 02:22:22AM +0800, Icenowy Zheng wrote:
> >> 21.03.2017, 15:41, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> >> > On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
> >> >> Many Allwinner SoCs after A31 have a CCU in PRCM block.
> >> >>
> >> >> Give the ones on H3 and A64 compatible strings.
> >> >>
> >> >> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> >> >> ---
> >> >> Changes in v2:
> >> >> - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
> >> >> clock for mux 3 of ar100 clk. Investgations are needed for them.)
> >> >>
> >> >> Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
> >> >> 1 file changed, 17 insertions(+), 1 deletion(-)
> >> >>
> >> >> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> >> index 68512aa398a9..4a4addff595d 100644
> >> >> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> >> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> >> @@ -7,9 +7,11 @@ Required properties :
> >> >> - "allwinner,sun8i-a23-ccu"
> >> >> - "allwinner,sun8i-a33-ccu"
> >> >> - "allwinner,sun8i-h3-ccu"
> >> >> + - "allwinner,sun8i-h3-r-ccu"
> >> >> - "allwinner,sun8i-v3s-ccu"
> >> >> - "allwinner,sun9i-a80-ccu"
> >> >> - "allwinner,sun50i-a64-ccu"
> >> >> + - "allwinner,sun50i-a64-r-ccu"
> >> >> - "allwinner,sun50i-h5-ccu"
> >> >>
> >> >> - reg: Must contain the registers base address and length
> >> >> @@ -20,7 +22,11 @@ Required properties :
> >> >> - #clock-cells : must contain 1
> >> >> - #reset-cells : must contain 1
> >> >>
> >> >> -Example:
> >> >> +For the PRCM CCUs on H3/A64, one more clock is needed:
> >> >> +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
> >> >> + not the same with losc)
> >> >
> >> > This is called the internal oscillator in the datasheet, it would
> >> > probably make more sense to call it that way in the documentation too.
> >> >
> >> > This oscillator seems to be clocked at 16MHz, so we should represent
> >> > it as such.
> >> >
> >> > And I'm wondering, are you *sure* that it's fed directly from the
> >> > internal oscillator, or goes through the registers in the RTC, with
> >> > the 32 divider and 16 prescaler by default that makes it at roughly
> >> > the same rate (31.25kHz).
> >>
> >> In fact I know nothing about it -- I only represented the code in BSP
> >> clock driver.
> >>
> >> The mux value 3 varies from SoC to SoC. For A64/H5 it's 32000,
> >> for A33 it's 667000 (seems to be directly the internal OSC, as the
> >> user manual says the internal OSC is 600~700kHz; but it's named
> >> cpuosc rather than iosc in A33 BSP clock driver); for A80 it's even
> >> PLL_AUDIO.
> >
> > Where are you getting those info from?
> >
> > As far as I know, the A33 PRCM takes the hosc, losc, pll6 and CPU
> > (internal) oscillator:
> > https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L508
> >
> > The H3 takes the hosc and losc:
> > https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw7.c#L379
> >
> > The A80 takes the hosc and losc:
> > https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun9iw1.c#L281
> >
> > The A64 takes the hosc, losc, pll-periph0 and the iosc, which indeed
> > seems to be fed from the internal oscillator with the divider in the
> > RTC:
> > https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/arch/arm64/boot/dts/sun50iw1p1-clk.dtsi#L19
> > https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/drivers/clk/sunxi/clk-sun50iw1.c#L603
>
> But then in sunxi_init_clocks function, the iosc clock is initialized
> as a fixed clock with 32000Hz.
>
> The clock node in BSP device tree have a compatible of
> allwinner,fixed-clock, but not fixed-clock, which makes it not able
> to be really probed.
That clock is registered:
https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/drivers/clk/sunxi/clk-sun50iw1.c#L1193
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs
@ 2017-03-26 13:10 ` Maxime Ripard
0 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2017-03-26 13:10 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 23, 2017 at 07:17:03AM +0800, Icenowy Zheng wrote:
>
>
> 23.03.2017, 04:09, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> > On Wed, Mar 22, 2017 at 02:22:22AM +0800, Icenowy Zheng wrote:
> >> ?21.03.2017, 15:41, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> >> ?> On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote:
> >> ?>> ?Many Allwinner SoCs after A31 have a CCU in PRCM block.
> >> ?>>
> >> ?>> ?Give the ones on H3 and A64 compatible strings.
> >> ?>>
> >> ?>> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >> ?>> ?---
> >> ?>> ?Changes in v2:
> >> ?>> ?- Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different
> >> ?>> ???clock for mux 3 of ar100 clk. Investgations are needed for them.)
> >> ?>>
> >> ?>> ??Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++-
> >> ?>> ??1 file changed, 17 insertions(+), 1 deletion(-)
> >> ?>>
> >> ?>> ?diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> ?>> ?index 68512aa398a9..4a4addff595d 100644
> >> ?>> ?--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> ?>> ?+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> >> ?>> ?@@ -7,9 +7,11 @@ Required properties :
> >> ?>> ??????????????????- "allwinner,sun8i-a23-ccu"
> >> ?>> ??????????????????- "allwinner,sun8i-a33-ccu"
> >> ?>> ??????????????????- "allwinner,sun8i-h3-ccu"
> >> ?>> ?+ - "allwinner,sun8i-h3-r-ccu"
> >> ?>> ??????????????????- "allwinner,sun8i-v3s-ccu"
> >> ?>> ??????????????????- "allwinner,sun9i-a80-ccu"
> >> ?>> ??????????????????- "allwinner,sun50i-a64-ccu"
> >> ?>> ?+ - "allwinner,sun50i-a64-r-ccu"
> >> ?>> ??????????????????- "allwinner,sun50i-h5-ccu"
> >> ?>>
> >> ?>> ??- reg: Must contain the registers base address and length
> >> ?>> ?@@ -20,7 +22,11 @@ Required properties :
> >> ?>> ??- #clock-cells : must contain 1
> >> ?>> ??- #reset-cells : must contain 1
> >> ?>>
> >> ?>> ?-Example:
> >> ?>> ?+For the PRCM CCUs on H3/A64, one more clock is needed:
> >> ?>> ?+- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz,
> >> ?>> ?+ not the same with losc)
> >> ?>
> >> ?> This is called the internal oscillator in the datasheet, it would
> >> ?> probably make more sense to call it that way in the documentation too.
> >> ?>
> >> ?> This oscillator seems to be clocked at 16MHz, so we should represent
> >> ?> it as such.
> >> ?>
> >> ?> And I'm wondering, are you *sure* that it's fed directly from the
> >> ?> internal oscillator, or goes through the registers in the RTC, with
> >> ?> the 32 divider and 16 prescaler by default that makes it at roughly
> >> ?> the same rate (31.25kHz).
> >>
> >> ?In fact I know nothing about it -- I only represented the code in BSP
> >> ?clock driver.
> >>
> >> ?The mux value 3 varies from SoC to SoC. For A64/H5 it's 32000,
> >> ?for A33 it's 667000 (seems to be directly the internal OSC, as the
> >> ?user manual says the internal OSC is 600~700kHz; but it's named
> >> ?cpuosc rather than iosc in A33 BSP clock driver); for A80 it's even
> >> ?PLL_AUDIO.
> >
> > Where are you getting those info from?
> >
> > As far as I know, the A33 PRCM takes the hosc, losc, pll6 and CPU
> > (internal) oscillator:
> > https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L508
> >
> > The H3 takes the hosc and losc:
> > https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw7.c#L379
> >
> > The A80 takes the hosc and losc:
> > https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun9iw1.c#L281
> >
> > The A64 takes the hosc, losc, pll-periph0 and the iosc, which indeed
> > seems to be fed from the internal oscillator with the divider in the
> > RTC:
> > https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/arch/arm64/boot/dts/sun50iw1p1-clk.dtsi#L19
> > https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/drivers/clk/sunxi/clk-sun50iw1.c#L603
>
> But then in sunxi_init_clocks function, the iosc clock is initialized
> as a fixed clock with 32000Hz.
>
> The clock node in BSP device tree have a compatible of
> allwinner,fixed-clock, but not fixed-clock, which makes it not able
> to be really probed.
That clock is registered:
https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/drivers/clk/sunxi/clk-sun50iw1.c#L1193
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2017-03-27 8:54 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-15 17:28 [PATCH v2 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs Icenowy Zheng
2017-03-15 17:28 ` Icenowy Zheng
[not found] ` <20170315172808.64011-1-icenowy-ymACFijhrKM@public.gmane.org>
2017-03-15 17:28 ` [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs Icenowy Zheng
2017-03-15 17:28 ` Icenowy Zheng
2017-03-21 7:41 ` Maxime Ripard
2017-03-21 7:41 ` Maxime Ripard
2017-03-21 7:41 ` Maxime Ripard
2017-03-21 18:22 ` Icenowy Zheng
2017-03-21 18:22 ` Icenowy Zheng
2017-03-22 20:09 ` Maxime Ripard
2017-03-22 20:09 ` Maxime Ripard
2017-03-22 20:09 ` Maxime Ripard
2017-03-22 23:17 ` Icenowy Zheng
2017-03-22 23:17 ` Icenowy Zheng
2017-03-26 13:10 ` Maxime Ripard
2017-03-26 13:10 ` Maxime Ripard
2017-03-26 13:10 ` Maxime Ripard
2017-03-15 17:28 ` [PATCH v2 2/5] clk: sunxi-ng: add support for " Icenowy Zheng
2017-03-15 17:28 ` Icenowy Zheng
2017-03-15 17:28 ` [PATCH v2 3/5] arm64: allwinner: a64: add r_ccu node Icenowy Zheng
2017-03-15 17:28 ` Icenowy Zheng
2017-03-15 17:28 ` [PATCH v2 4/5] ARM: sun8i: h3: switch apb0-related clocks to r_ccu Icenowy Zheng
2017-03-15 17:28 ` Icenowy Zheng
2017-03-15 17:28 ` [PATCH v2 5/5] arm64: allwinner: a64: add R_PIO pinctrl node Icenowy Zheng
2017-03-15 17:28 ` Icenowy Zheng
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