From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751235AbdCQLNR (ORCPT ); Fri, 17 Mar 2017 07:13:17 -0400 Received: from mga06.intel.com ([134.134.136.31]:37406 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751191AbdCQLNP (ORCPT ); Fri, 17 Mar 2017 07:13:15 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,176,1486454400"; d="scan'208";a="77568399" Date: Fri, 17 Mar 2017 16:43:11 +0530 From: Rajneesh Bhardwaj To: Kuppuswamy Sathyanarayanan Cc: andy@infradead.org, qipeng.zha@intel.com, dvhart@infradead.org, david.e.box@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, shanth.murthy@intel.com Subject: Re: [PATCH v2 1/4] platform/x86: intel_pmc_ipc: fix gcr offset Message-ID: <20170317111310.GC24582@rajaneesh-OptiPlex-9010> References: <20170316192003.GA19344@rajaneesh-OptiPlex-9010> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 16, 2017 at 05:41:33PM -0700, Kuppuswamy Sathyanarayanan wrote: > According to the PMC spec, gcr offset from ipc mem > region is 0x1000(4K). But currently this driver uses > 0x1008 as gcr offset. This patch fixes this issue. > This one is fine and was one of the WIP patches. This now enables further cleanup and we should re-align GCR_TELEM_DEEP_S0IX_OFFSET from gcr_base. CC: Shanth Murthy > Signed-off-by: Kuppuswamy Sathyanarayanan > --- > drivers/platform/x86/intel_pmc_ipc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c > index 0651d47..0a33592 100644 > --- a/drivers/platform/x86/intel_pmc_ipc.c > +++ b/drivers/platform/x86/intel_pmc_ipc.c > @@ -82,7 +82,7 @@ > /* exported resources from IFWI */ > #define PLAT_RESOURCE_IPC_INDEX 0 > #define PLAT_RESOURCE_IPC_SIZE 0x1000 > -#define PLAT_RESOURCE_GCR_OFFSET 0x1008 > +#define PLAT_RESOURCE_GCR_OFFSET 0x1000 > #define PLAT_RESOURCE_GCR_SIZE 0x1000 > #define PLAT_RESOURCE_BIOS_DATA_INDEX 1 > #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2 > -- > 2.7.4 > -- Best Regards, Rajneesh From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rajneesh Bhardwaj Subject: Re: [PATCH v2 1/4] platform/x86: intel_pmc_ipc: fix gcr offset Date: Fri, 17 Mar 2017 16:43:11 +0530 Message-ID: <20170317111310.GC24582@rajaneesh-OptiPlex-9010> References: <20170316192003.GA19344@rajaneesh-OptiPlex-9010> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Kuppuswamy Sathyanarayanan Cc: andy@infradead.org, qipeng.zha@intel.com, dvhart@infradead.org, david.e.box@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, shanth.murthy@intel.com List-Id: platform-driver-x86.vger.kernel.org On Thu, Mar 16, 2017 at 05:41:33PM -0700, Kuppuswamy Sathyanarayanan wrote: > According to the PMC spec, gcr offset from ipc mem > region is 0x1000(4K). But currently this driver uses > 0x1008 as gcr offset. This patch fixes this issue. > This one is fine and was one of the WIP patches. This now enables further cleanup and we should re-align GCR_TELEM_DEEP_S0IX_OFFSET from gcr_base. CC: Shanth Murthy > Signed-off-by: Kuppuswamy Sathyanarayanan > --- > drivers/platform/x86/intel_pmc_ipc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c > index 0651d47..0a33592 100644 > --- a/drivers/platform/x86/intel_pmc_ipc.c > +++ b/drivers/platform/x86/intel_pmc_ipc.c > @@ -82,7 +82,7 @@ > /* exported resources from IFWI */ > #define PLAT_RESOURCE_IPC_INDEX 0 > #define PLAT_RESOURCE_IPC_SIZE 0x1000 > -#define PLAT_RESOURCE_GCR_OFFSET 0x1008 > +#define PLAT_RESOURCE_GCR_OFFSET 0x1000 > #define PLAT_RESOURCE_GCR_SIZE 0x1000 > #define PLAT_RESOURCE_BIOS_DATA_INDEX 1 > #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2 > -- > 2.7.4 > -- Best Regards, Rajneesh