From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751200AbdCQL0p (ORCPT ); Fri, 17 Mar 2017 07:26:45 -0400 Received: from mga06.intel.com ([134.134.136.31]:44933 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751021AbdCQL0m (ORCPT ); Fri, 17 Mar 2017 07:26:42 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,176,1486454400"; d="scan'208";a="1123970425" Date: Fri, 17 Mar 2017 16:56:33 +0530 From: Rajneesh Bhardwaj To: Kuppuswamy Sathyanarayanan Cc: andy@infradead.org, qipeng.zha@intel.com, dvhart@infradead.org, david.e.box@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, shanth.murthy@intel.com Subject: Re: [PATCH v2 2/4] platform/x86: intel_pmc_ipc: Add pmc gcr read/write api's Message-ID: <20170317112633.GD24582@rajaneesh-OptiPlex-9010> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 16, 2017 at 05:41:34PM -0700, Kuppuswamy Sathyanarayanan wrote: > This patch adds API's to read/write PMC GC registers. > PMC dependent devices like iTCO_WDT, Telemetry has requirement > to acces GCR registers. These API's can be used for this > purpose. > > Signed-off-by: Kuppuswamy Sathyanarayanan > --- > arch/x86/include/asm/intel_pmc_ipc.h | 16 ++++++++++++++++ > drivers/platform/x86/intel_pmc_ipc.c | 14 ++++++++++++++ > 2 files changed, 30 insertions(+) > > diff --git a/arch/x86/include/asm/intel_pmc_ipc.h b/arch/x86/include/asm/intel_pmc_ipc.h > index 4291b6a..017429d 100644 > --- a/arch/x86/include/asm/intel_pmc_ipc.h > +++ b/arch/x86/include/asm/intel_pmc_ipc.h > @@ -23,6 +23,10 @@ > #define IPC_ERR_EMSECURITY 6 > #define IPC_ERR_UNSIGNEDKERNEL 7 > > +/* GCR reg offsets from gcr base*/ > +#define PMC_GCR_PRSTS_REG 0x00 remove. > +#define PMC_GCR_PMC_CFG_REG 0x08 > + > #if IS_ENABLED(CONFIG_INTEL_PMC_IPC) > > int intel_pmc_ipc_simple_command(int cmd, int sub); > @@ -31,6 +35,8 @@ int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, > int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen, > u32 *out, u32 outlen); > int intel_pmc_s0ix_counter_read(u64 *data); > +u32 intel_pmc_gcr_read(u32 offset); consider changing the signature to read data as out param and use return value for better error handling since exported API can be called from anywhere in the kernel. > +void intel_pmc_gcr_write(u32 offset, u32 data); ditto. > > #else > > @@ -56,6 +62,16 @@ static inline int intel_pmc_s0ix_counter_read(u64 *data) > return -EINVAL; > } > > +static inline u32 intel_pmc_gcr_read(u32 offset) > +{ > + return -EINVAL; > +} > + samew as above. > +static inline void intel_pmc_gcr_write(u32 offset, u32 data) > +{ > + return; > +} > + ditto. > #endif /*CONFIG_INTEL_PMC_IPC*/ > > #endif > diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c > index 0a33592..12018f3 100644 > --- a/drivers/platform/x86/intel_pmc_ipc.c > +++ b/drivers/platform/x86/intel_pmc_ipc.c > @@ -127,6 +127,7 @@ static struct intel_pmc_ipc_dev { > > /* gcr */ > resource_size_t gcr_base; > + void __iomem *gcr_mem_base; > int gcr_size; > bool has_gcr_regs; > > @@ -199,6 +200,18 @@ static inline u64 gcr_data_readq(u32 offset) > return readq(ipcdev.ipc_base + offset); > } > > +u32 intel_pmc_gcr_read(u32 offset) > +{ > + return readl(ipcdev.gcr_mem_base + offset); > +} what happens when this is called with a wrong offset on IPC enabled platforms? > +EXPORT_SYMBOL_GPL(intel_pmc_gcr_read); > + > +void intel_pmc_gcr_write(u32 offset, u32 data) > +{ > + writel(data, ipcdev.gcr_mem_base + offset); > +} same as above. > +EXPORT_SYMBOL_GPL(intel_pmc_gcr_write); > + > static int intel_pmc_ipc_check_status(void) > { > int status; > @@ -747,6 +760,7 @@ static int ipc_plat_get_res(struct platform_device *pdev) > ipcdev.ipc_base = addr; > > ipcdev.gcr_base = res->start + PLAT_RESOURCE_GCR_OFFSET; > + ipcdev.gcr_mem_base = addr + PLAT_RESOURCE_GCR_OFFSET; > ipcdev.gcr_size = PLAT_RESOURCE_GCR_SIZE; > dev_info(&pdev->dev, "ipc res: %pR\n", res); > > -- > 2.7.4 > -- Best Regards, Rajneesh From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rajneesh Bhardwaj Subject: Re: [PATCH v2 2/4] platform/x86: intel_pmc_ipc: Add pmc gcr read/write api's Date: Fri, 17 Mar 2017 16:56:33 +0530 Message-ID: <20170317112633.GD24582@rajaneesh-OptiPlex-9010> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Kuppuswamy Sathyanarayanan Cc: andy@infradead.org, qipeng.zha@intel.com, dvhart@infradead.org, david.e.box@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, shanth.murthy@intel.com List-Id: platform-driver-x86.vger.kernel.org On Thu, Mar 16, 2017 at 05:41:34PM -0700, Kuppuswamy Sathyanarayanan wrote: > This patch adds API's to read/write PMC GC registers. > PMC dependent devices like iTCO_WDT, Telemetry has requirement > to acces GCR registers. These API's can be used for this > purpose. > > Signed-off-by: Kuppuswamy Sathyanarayanan > --- > arch/x86/include/asm/intel_pmc_ipc.h | 16 ++++++++++++++++ > drivers/platform/x86/intel_pmc_ipc.c | 14 ++++++++++++++ > 2 files changed, 30 insertions(+) > > diff --git a/arch/x86/include/asm/intel_pmc_ipc.h b/arch/x86/include/asm/intel_pmc_ipc.h > index 4291b6a..017429d 100644 > --- a/arch/x86/include/asm/intel_pmc_ipc.h > +++ b/arch/x86/include/asm/intel_pmc_ipc.h > @@ -23,6 +23,10 @@ > #define IPC_ERR_EMSECURITY 6 > #define IPC_ERR_UNSIGNEDKERNEL 7 > > +/* GCR reg offsets from gcr base*/ > +#define PMC_GCR_PRSTS_REG 0x00 remove. > +#define PMC_GCR_PMC_CFG_REG 0x08 > + > #if IS_ENABLED(CONFIG_INTEL_PMC_IPC) > > int intel_pmc_ipc_simple_command(int cmd, int sub); > @@ -31,6 +35,8 @@ int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, > int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen, > u32 *out, u32 outlen); > int intel_pmc_s0ix_counter_read(u64 *data); > +u32 intel_pmc_gcr_read(u32 offset); consider changing the signature to read data as out param and use return value for better error handling since exported API can be called from anywhere in the kernel. > +void intel_pmc_gcr_write(u32 offset, u32 data); ditto. > > #else > > @@ -56,6 +62,16 @@ static inline int intel_pmc_s0ix_counter_read(u64 *data) > return -EINVAL; > } > > +static inline u32 intel_pmc_gcr_read(u32 offset) > +{ > + return -EINVAL; > +} > + samew as above. > +static inline void intel_pmc_gcr_write(u32 offset, u32 data) > +{ > + return; > +} > + ditto. > #endif /*CONFIG_INTEL_PMC_IPC*/ > > #endif > diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c > index 0a33592..12018f3 100644 > --- a/drivers/platform/x86/intel_pmc_ipc.c > +++ b/drivers/platform/x86/intel_pmc_ipc.c > @@ -127,6 +127,7 @@ static struct intel_pmc_ipc_dev { > > /* gcr */ > resource_size_t gcr_base; > + void __iomem *gcr_mem_base; > int gcr_size; > bool has_gcr_regs; > > @@ -199,6 +200,18 @@ static inline u64 gcr_data_readq(u32 offset) > return readq(ipcdev.ipc_base + offset); > } > > +u32 intel_pmc_gcr_read(u32 offset) > +{ > + return readl(ipcdev.gcr_mem_base + offset); > +} what happens when this is called with a wrong offset on IPC enabled platforms? > +EXPORT_SYMBOL_GPL(intel_pmc_gcr_read); > + > +void intel_pmc_gcr_write(u32 offset, u32 data) > +{ > + writel(data, ipcdev.gcr_mem_base + offset); > +} same as above. > +EXPORT_SYMBOL_GPL(intel_pmc_gcr_write); > + > static int intel_pmc_ipc_check_status(void) > { > int status; > @@ -747,6 +760,7 @@ static int ipc_plat_get_res(struct platform_device *pdev) > ipcdev.ipc_base = addr; > > ipcdev.gcr_base = res->start + PLAT_RESOURCE_GCR_OFFSET; > + ipcdev.gcr_mem_base = addr + PLAT_RESOURCE_GCR_OFFSET; > ipcdev.gcr_size = PLAT_RESOURCE_GCR_SIZE; > dev_info(&pdev->dev, "ipc res: %pR\n", res); > > -- > 2.7.4 > -- Best Regards, Rajneesh