From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751239AbdCRUXh (ORCPT ); Sat, 18 Mar 2017 16:23:37 -0400 Received: from mail-qk0-f193.google.com ([209.85.220.193]:33324 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751179AbdCRUXe (ORCPT ); Sat, 18 Mar 2017 16:23:34 -0400 From: Ilia Mirkin To: Ben Skeggs , Dave Airlie Cc: dri-devel@lists.freedesktop.org, nouveau@lists.freedesktop.org, linux-kernel@vger.kernel.org, Ilia Mirkin Subject: [PATCH] drm/nouveau/mmu/nv4a: use nv04 mmu rather than the nv44 one Date: Sat, 18 Mar 2017 16:23:10 -0400 Message-Id: <20170318202310.4940-1-imirkin@alum.mit.edu> X-Mailer: git-send-email 2.10.2 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The NV4A (aka NV44A) is an oddity in the family. It only comes in AGP and PCI varieties, rather than a core PCIE chip with a bridge for AGP/PCI as necessary. As a result, it appears that the MMU is also non-functional. For AGP cards, the vast majority of the NV4A lineup, this worked out since we force AGP cards to use the nv04 mmu. However for PCI variants, this did not work. Switching to the NV04 MMU makes it work like a charm. Thanks to mwk for the suggestion. This should be a no-op for NV4A AGP boards, as they were using it already. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70388 Signed-off-by: Ilia Mirkin Cc: stable@vger.kernel.org --- OK, so I'm not 100% sure about my claims, but I don't have the necessary hardware to test it out. Right now, AGP nv41+ boards are getting the nv04 mmu, while PCI nv41+ boards are getting the PCIE one. Perhaps this works for them, however such boards are rare, and I don't have one. Perhaps all PCI boards should be routed to the nv04 mmu, not just the NV4A ones. drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 273562d..0fc41db 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -714,7 +714,7 @@ nv4a_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv44_mc_new, - .mmu = nv44_mmu_new, + .mmu = nv04_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, .timer = nv41_timer_new, -- 2.10.2 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ilia Mirkin Subject: [PATCH] drm/nouveau/mmu/nv4a: use nv04 mmu rather than the nv44 one Date: Sat, 18 Mar 2017 16:23:10 -0400 Message-ID: <20170318202310.4940-1-imirkin@alum.mit.edu> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Ben Skeggs , Dave Airlie Cc: nouveau@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org List-Id: nouveau.vger.kernel.org VGhlIE5WNEEgKGFrYSBOVjQ0QSkgaXMgYW4gb2RkaXR5IGluIHRoZSBmYW1pbHkuIEl0IG9ubHkg Y29tZXMgaW4gQUdQCmFuZCBQQ0kgdmFyaWV0aWVzLCByYXRoZXIgdGhhbiBhIGNvcmUgUENJRSBj aGlwIHdpdGggYSBicmlkZ2UgZm9yCkFHUC9QQ0kgYXMgbmVjZXNzYXJ5LiBBcyBhIHJlc3VsdCwg aXQgYXBwZWFycyB0aGF0IHRoZSBNTVUgaXMgYWxzbwpub24tZnVuY3Rpb25hbC4gRm9yIEFHUCBj YXJkcywgdGhlIHZhc3QgbWFqb3JpdHkgb2YgdGhlIE5WNEEgbGluZXVwLAp0aGlzIHdvcmtlZCBv dXQgc2luY2Ugd2UgZm9yY2UgQUdQIGNhcmRzIHRvIHVzZSB0aGUgbnYwNCBtbXUuIEhvd2V2ZXIK Zm9yIFBDSSB2YXJpYW50cywgdGhpcyBkaWQgbm90IHdvcmsuCgpTd2l0Y2hpbmcgdG8gdGhlIE5W MDQgTU1VIG1ha2VzIGl0IHdvcmsgbGlrZSBhIGNoYXJtLiBUaGFua3MgdG8gbXdrIGZvcgp0aGUg c3VnZ2VzdGlvbi4gVGhpcyBzaG91bGQgYmUgYSBuby1vcCBmb3IgTlY0QSBBR1AgYm9hcmRzLCBh cyB0aGV5IHdlcmUKdXNpbmcgaXQgYWxyZWFkeS4KCkJ1Z3ppbGxhOiBodHRwczovL2J1Z3MuZnJl ZWRlc2t0b3Aub3JnL3Nob3dfYnVnLmNnaT9pZD03MDM4OApTaWduZWQtb2ZmLWJ5OiBJbGlhIE1p cmtpbiA8aW1pcmtpbkBhbHVtLm1pdC5lZHU+CkNjOiBzdGFibGVAdmdlci5rZXJuZWwub3JnCi0t LQoKT0ssIHNvIEknbSBub3QgMTAwJSBzdXJlIGFib3V0IG15IGNsYWltcywgYnV0IEkgZG9uJ3Qg aGF2ZSB0aGUgbmVjZXNzYXJ5CmhhcmR3YXJlIHRvIHRlc3QgaXQgb3V0LiBSaWdodCBub3csIEFH UCBudjQxKyBib2FyZHMgYXJlIGdldHRpbmcgdGhlIG52MDQKbW11LCB3aGlsZSBQQ0kgbnY0MSsg Ym9hcmRzIGFyZSBnZXR0aW5nIHRoZSBQQ0lFIG9uZS4gUGVyaGFwcyB0aGlzIHdvcmtzCmZvciB0 aGVtLCBob3dldmVyIHN1Y2ggYm9hcmRzIGFyZSByYXJlLCBhbmQgSSBkb24ndCBoYXZlIG9uZS4g UGVyaGFwcyBhbGwKUENJIGJvYXJkcyBzaG91bGQgYmUgcm91dGVkIHRvIHRoZSBudjA0IG1tdSwg bm90IGp1c3QgdGhlIE5WNEEgb25lcy4KCiBkcml2ZXJzL2dwdS9kcm0vbm91dmVhdS9udmttL2Vu Z2luZS9kZXZpY2UvYmFzZS5jIHwgMiArLQogMSBmaWxlIGNoYW5nZWQsIDEgaW5zZXJ0aW9uKCsp LCAxIGRlbGV0aW9uKC0pCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL25vdXZlYXUvbnZr bS9lbmdpbmUvZGV2aWNlL2Jhc2UuYyBiL2RyaXZlcnMvZ3B1L2RybS9ub3V2ZWF1L252a20vZW5n aW5lL2RldmljZS9iYXNlLmMKaW5kZXggMjczNTYyZC4uMGZjNDFkYiAxMDA2NDQKLS0tIGEvZHJp dmVycy9ncHUvZHJtL25vdXZlYXUvbnZrbS9lbmdpbmUvZGV2aWNlL2Jhc2UuYworKysgYi9kcml2 ZXJzL2dwdS9kcm0vbm91dmVhdS9udmttL2VuZ2luZS9kZXZpY2UvYmFzZS5jCkBAIC03MTQsNyAr NzE0LDcgQEAgbnY0YV9jaGlwc2V0ID0gewogCS5pMmMgPSBudjA0X2kyY19uZXcsCiAJLmltZW0g PSBudjQwX2luc3RtZW1fbmV3LAogCS5tYyA9IG52NDRfbWNfbmV3LAotCS5tbXUgPSBudjQ0X21t dV9uZXcsCisJLm1tdSA9IG52MDRfbW11X25ldywKIAkucGNpID0gbnY0MF9wY2lfbmV3LAogCS50 aGVybSA9IG52NDBfdGhlcm1fbmV3LAogCS50aW1lciA9IG52NDFfdGltZXJfbmV3LAotLSAKMi4x MC4yCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmkt ZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6 Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK