From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756753AbdCUHlg (ORCPT ); Tue, 21 Mar 2017 03:41:36 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:46972 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756260AbdCUHle (ORCPT ); Tue, 21 Mar 2017 03:41:34 -0400 Date: Tue, 21 Mar 2017 08:41:17 +0100 From: Maxime Ripard To: Icenowy Zheng Cc: Rob Herring , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs Message-ID: <20170321074117.vdfjynauuuv6fivp@lukather> References: <20170315172808.64011-1-icenowy@aosc.xyz> <20170315172808.64011-2-icenowy@aosc.xyz> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="nlfme6nxrfyk26rd" Content-Disposition: inline In-Reply-To: <20170315172808.64011-2-icenowy@aosc.xyz> User-Agent: Mutt/1.6.2-neo (2016-08-21) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --nlfme6nxrfyk26rd Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote: > Many Allwinner SoCs after A31 have a CCU in PRCM block. >=20 > Give the ones on H3 and A64 compatible strings. >=20 > Signed-off-by: Icenowy Zheng > --- > Changes in v2: > - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different > clock for mux 3 of ar100 clk. Investgations are needed for them.) >=20 > Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++= ++++- > 1 file changed, 17 insertions(+), 1 deletion(-) >=20 > diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Docu= mentation/devicetree/bindings/clock/sunxi-ccu.txt > index 68512aa398a9..4a4addff595d 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > @@ -7,9 +7,11 @@ Required properties : > - "allwinner,sun8i-a23-ccu" > - "allwinner,sun8i-a33-ccu" > - "allwinner,sun8i-h3-ccu" > + - "allwinner,sun8i-h3-r-ccu" > - "allwinner,sun8i-v3s-ccu" > - "allwinner,sun9i-a80-ccu" > - "allwinner,sun50i-a64-ccu" > + - "allwinner,sun50i-a64-r-ccu" > - "allwinner,sun50i-h5-ccu" > =20 > - reg: Must contain the registers base address and length > @@ -20,7 +22,11 @@ Required properties : > - #clock-cells : must contain 1 > - #reset-cells : must contain 1 > =20 > -Example: > +For the PRCM CCUs on H3/A64, one more clock is needed: > +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz, > + not the same with losc) This is called the internal oscillator in the datasheet, it would probably make more sense to call it that way in the documentation too. This oscillator seems to be clocked at 16MHz, so we should represent it as such. And I'm wondering, are you *sure* that it's fed directly from the internal oscillator, or goes through the registers in the RTC, with the 32 divider and 16 prescaler by default that makes it at roughly the same rate (31.25kHz). Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --nlfme6nxrfyk26rd Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAEBCAAGBQJY0NkaAAoJEBx+YmzsjxAgvkYP/3N5u7SpSeejSBvUwczwaLig /8VC+itx4kOSYUrvlXrWX1uvZrpZCr/tv7OPG9/S5+9KVxAT/gVO1vopc/w8mjdT Yl1uQaKYjZ/p3329xEO/L/TSYLWjvWSLG+63BgOAUy4vzNGFPswQ0Tt5J/XaMtxU /EOAG5/fZ7Q5939w8sF6pJRpYyzHPd7YGya9qNjlxsKbLcZwkbVHxmBJQYLzyUDA H5sL6cW/1+BqCRwUquWQQtgoCrAAJTz5UVny9aqRj7uRFvSzTYq36s7B/FQePFLu yLCXOI5aZww6yYS8IBWAhHcS424NJSW0+SF47/3c5pbxVfkFDd22fx7lXGaUER1d r5eoBYZg0lm9aYPEyxa96Mi+o7M/sLMeikS5t03VyQE6KA6DK8akx/7CR4hGNmgp DuvyGky2LZpxFXecAfrZFe3eV6Gz/xIoB9BVgfZNF1mXskvcOVSBKfj/EjtQsoKp h8g/zG/dLYVPxLLfH6aax4nkTWtgLWcSvE7iYPd265enmWq6igVjXDFPrTScghDE g4vHihbR/uk9m9thwJFJ8M/jy6o1sEbcXc6F4Gxf32c+jqv656KbSbF60pxRg3/O xNakovAZslBw+5aZVuS8W6l7Ij+LR+f71xnXGSZUFmGemqucwZyeLLbYECI3h/IG pCXuj4Zmd9A4VaaIsDix =Q5Cn -----END PGP SIGNATURE----- --nlfme6nxrfyk26rd-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs Date: Tue, 21 Mar 2017 08:41:17 +0100 Message-ID: <20170321074117.vdfjynauuuv6fivp@lukather> References: <20170315172808.64011-1-icenowy@aosc.xyz> <20170315172808.64011-2-icenowy@aosc.xyz> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="nlfme6nxrfyk26rd" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20170315172808.64011-2-icenowy-ymACFijhrKM@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Icenowy Zheng Cc: Rob Herring , Chen-Yu Tsai , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: devicetree@vger.kernel.org --nlfme6nxrfyk26rd Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote: > Many Allwinner SoCs after A31 have a CCU in PRCM block. > > Give the ones on H3 and A64 compatible strings. > > Signed-off-by: Icenowy Zheng > --- > Changes in v2: > - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different > clock for mux 3 of ar100 clk. Investgations are needed for them.) > > Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > index 68512aa398a9..4a4addff595d 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > @@ -7,9 +7,11 @@ Required properties : > - "allwinner,sun8i-a23-ccu" > - "allwinner,sun8i-a33-ccu" > - "allwinner,sun8i-h3-ccu" > + - "allwinner,sun8i-h3-r-ccu" > - "allwinner,sun8i-v3s-ccu" > - "allwinner,sun9i-a80-ccu" > - "allwinner,sun50i-a64-ccu" > + - "allwinner,sun50i-a64-r-ccu" > - "allwinner,sun50i-h5-ccu" > > - reg: Must contain the registers base address and length > @@ -20,7 +22,11 @@ Required properties : > - #clock-cells : must contain 1 > - #reset-cells : must contain 1 > > -Example: > +For the PRCM CCUs on H3/A64, one more clock is needed: > +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz, > + not the same with losc) This is called the internal oscillator in the datasheet, it would probably make more sense to call it that way in the documentation too. This oscillator seems to be clocked at 16MHz, so we should represent it as such. And I'm wondering, are you *sure* that it's fed directly from the internal oscillator, or goes through the registers in the RTC, with the 32 divider and 16 prescaler by default that makes it at roughly the same rate (31.25kHz). Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --nlfme6nxrfyk26rd-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Tue, 21 Mar 2017 08:41:17 +0100 Subject: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs In-Reply-To: <20170315172808.64011-2-icenowy@aosc.xyz> References: <20170315172808.64011-1-icenowy@aosc.xyz> <20170315172808.64011-2-icenowy@aosc.xyz> Message-ID: <20170321074117.vdfjynauuuv6fivp@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote: > Many Allwinner SoCs after A31 have a CCU in PRCM block. > > Give the ones on H3 and A64 compatible strings. > > Signed-off-by: Icenowy Zheng > --- > Changes in v2: > - Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have different > clock for mux 3 of ar100 clk. Investgations are needed for them.) > > Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > index 68512aa398a9..4a4addff595d 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > @@ -7,9 +7,11 @@ Required properties : > - "allwinner,sun8i-a23-ccu" > - "allwinner,sun8i-a33-ccu" > - "allwinner,sun8i-h3-ccu" > + - "allwinner,sun8i-h3-r-ccu" > - "allwinner,sun8i-v3s-ccu" > - "allwinner,sun9i-a80-ccu" > - "allwinner,sun50i-a64-ccu" > + - "allwinner,sun50i-a64-r-ccu" > - "allwinner,sun50i-h5-ccu" > > - reg: Must contain the registers base address and length > @@ -20,7 +22,11 @@ Required properties : > - #clock-cells : must contain 1 > - #reset-cells : must contain 1 > > -Example: > +For the PRCM CCUs on H3/A64, one more clock is needed: > +- "iosc": another frequency oscillator used for CPUS (usually at 32000Hz, > + not the same with losc) This is called the internal oscillator in the datasheet, it would probably make more sense to call it that way in the documentation too. This oscillator seems to be clocked at 16MHz, so we should represent it as such. And I'm wondering, are you *sure* that it's fed directly from the internal oscillator, or goes through the registers in the RTC, with the 32 divider and 16 prescaler by default that makes it at roughly the same rate (31.25kHz). Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: