From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Tue, 21 Mar 2017 15:27:58 +0100 Subject: [U-Boot] [PATCH v1 37/41] net: mvpp2: Enable PHY polling mode on PPv2.2 In-Reply-To: <20170321142802.24276-1-sr@denx.de> References: <20170321142802.24276-1-sr@denx.de> Message-ID: <20170321142802.24276-38-sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Testing shows, that PHY polling needs to be enabled on Armada 7k/8k. Otherwise ethernet transfers will not work correctly. PHY polling is enabled per default after reset, so we do not need to specifically enable it, but this makes it clearer. Signed-off-by: Stefan Roese Cc: Stefan Chulski Cc: Kostya Porotchkin Cc: Nadav Haklai --- drivers/net/mvpp2.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index c940b95d05..6537ee3f92 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -5159,14 +5159,15 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv) if (priv->hw_version == MVPP22) mvpp2_axi_init(priv); - /* Disable HW PHY polling */ if (priv->hw_version == MVPP21) { + /* Disable HW PHY polling */ val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); val |= MVPP2_PHY_AN_STOP_SMI0_MASK; writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); } else { + /* Enable HW PHY polling */ val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); - val &= ~MVPP22_SMI_POLLING_EN; + val |= MVPP22_SMI_POLLING_EN; writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); } -- 2.12.0