From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Thu, 23 Mar 2017 17:02:07 +0100 Subject: [U-Boot] [PATCH v2 41/45] net: mvpp2: Enable PHY polling mode on PPv2.2 In-Reply-To: <20170323160211.18072-1-sr@denx.de> References: <20170323160211.18072-1-sr@denx.de> Message-ID: <20170323160211.18072-42-sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Testing shows, that PHY polling needs to be enabled on Armada 7k/8k. Otherwise ethernet transfers will not work correctly. PHY polling is enabled per default after reset, so we do not need to specifically enable it, but this makes it clearer. Signed-off-by: Stefan Roese Cc: Stefan Chulski Cc: Kostya Porotchkin Cc: Nadav Haklai Acked-by: Joe Hershberger --- Changes in v2: - Added Acked-by from Joe drivers/net/mvpp2.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index d20d82e017..cc6d42255c 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -4966,14 +4966,15 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv) if (priv->hw_version == MVPP22) mvpp2_axi_init(priv); - /* Disable HW PHY polling */ if (priv->hw_version == MVPP21) { + /* Disable HW PHY polling */ val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); val |= MVPP2_PHY_AN_STOP_SMI0_MASK; writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); } else { + /* Enable HW PHY polling */ val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); - val &= ~MVPP22_SMI_POLLING_EN; + val |= MVPP22_SMI_POLLING_EN; writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); } -- 2.12.1