From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935739AbdCXLvI (ORCPT ); Fri, 24 Mar 2017 07:51:08 -0400 Received: from foss.arm.com ([217.140.101.70]:39684 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752034AbdCXLvA (ORCPT ); Fri, 24 Mar 2017 07:51:00 -0400 Date: Fri, 24 Mar 2017 11:43:25 +0000 From: Mark Rutland To: Anurup M Cc: will.deacon@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, anurup.m@huawei.com, zhangshaokun@hisilicon.com, tanxiaojun@huawei.com, xuwei5@hisilicon.com, sanil.kumar@hisilicon.com, john.garry@huawei.com, gabriele.paoloni@huawei.com, shiju.jose@huawei.com, huangdaode@hisilicon.com, linuxarm@huawei.com, dikshit.n@huawei.com, shyju.pv@huawei.com Subject: Re: [PATCH v6 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow Message-ID: <20170324114325.GC22771@leverpostej> References: <1489127325-112821-1-git-send-email-anurup.m@huawei.com> <20170321171605.GB29116@leverpostej> <58D4C006.2010907@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <58D4C006.2010907@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Mar 24, 2017 at 12:13:18PM +0530, Anurup M wrote: > On Tuesday 21 March 2017 10:46 PM, Mark Rutland wrote: > >On Fri, Mar 10, 2017 at 01:28:45AM -0500, Anurup M wrote: > >>+/* The counter overflow IRQ is not supported for some PMUs > >>+ * use hrtimer to periodically poll and avoid overflow > >>+ */ > >>+static enum hrtimer_restart hisi_hrtimer_callback(struct hrtimer *hrtimer) > >>+{ > >>+ struct hisi_pmu *hisi_pmu = container_of(hrtimer, > >>+ struct hisi_pmu, hrtimer); > >>+ struct perf_event *event; > >>+ struct hw_perf_event *hwc; > >>+ unsigned long flags; > >>+ > >>+ /* Return if no active events */ > >>+ if (!hisi_pmu->num_active) > >>+ return HRTIMER_NORESTART; > >>+ > >>+ local_irq_save(flags); > >>+ > >>+ /* Update event count for each active event */ > >>+ list_for_each_entry(event, &hisi_pmu->active_list, active_entry) { > >>+ hwc = &event->hw; > >>+ /* Read hardware counter and update the Perf event counter */ > >>+ hisi_pmu->ops->event_update(event, hwc, GET_CNTR_IDX(hwc)); > >>+ } > >How do we ensure that we don't take the interrupt in the middle of a > >sequence of accesses to the HW? > > The L3 cache and MN PMU does not use the overflow IRQ and it does > not occur here > as the interrupt Mask register is by default masked in hardware. I was referring to the timer interrupt which backs the hrtimer. i.e. how do we guarantee that hisi_hrtimer_callback() is not called while we are in the middle of a RMW sequence? Are interrupts disabled for all of those seqeunces? Thanks, Mark. From mboxrd@z Thu Jan 1 00:00:00 1970 From: mark.rutland@arm.com (Mark Rutland) Date: Fri, 24 Mar 2017 11:43:25 +0000 Subject: [PATCH v6 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow In-Reply-To: <58D4C006.2010907@gmail.com> References: <1489127325-112821-1-git-send-email-anurup.m@huawei.com> <20170321171605.GB29116@leverpostej> <58D4C006.2010907@gmail.com> Message-ID: <20170324114325.GC22771@leverpostej> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Mar 24, 2017 at 12:13:18PM +0530, Anurup M wrote: > On Tuesday 21 March 2017 10:46 PM, Mark Rutland wrote: > >On Fri, Mar 10, 2017 at 01:28:45AM -0500, Anurup M wrote: > >>+/* The counter overflow IRQ is not supported for some PMUs > >>+ * use hrtimer to periodically poll and avoid overflow > >>+ */ > >>+static enum hrtimer_restart hisi_hrtimer_callback(struct hrtimer *hrtimer) > >>+{ > >>+ struct hisi_pmu *hisi_pmu = container_of(hrtimer, > >>+ struct hisi_pmu, hrtimer); > >>+ struct perf_event *event; > >>+ struct hw_perf_event *hwc; > >>+ unsigned long flags; > >>+ > >>+ /* Return if no active events */ > >>+ if (!hisi_pmu->num_active) > >>+ return HRTIMER_NORESTART; > >>+ > >>+ local_irq_save(flags); > >>+ > >>+ /* Update event count for each active event */ > >>+ list_for_each_entry(event, &hisi_pmu->active_list, active_entry) { > >>+ hwc = &event->hw; > >>+ /* Read hardware counter and update the Perf event counter */ > >>+ hisi_pmu->ops->event_update(event, hwc, GET_CNTR_IDX(hwc)); > >>+ } > >How do we ensure that we don't take the interrupt in the middle of a > >sequence of accesses to the HW? > > The L3 cache and MN PMU does not use the overflow IRQ and it does > not occur here > as the interrupt Mask register is by default masked in hardware. I was referring to the timer interrupt which backs the hrtimer. i.e. how do we guarantee that hisi_hrtimer_callback() is not called while we are in the middle of a RMW sequence? Are interrupts disabled for all of those seqeunces? Thanks, Mark.