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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org, Mika Kuoppala <mika.kuoppala@intel.com>
Subject: Re: [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush
Date: Fri, 24 Mar 2017 21:05:13 +0200	[thread overview]
Message-ID: <20170324190513.GF30290@intel.com> (raw)
In-Reply-To: <20170324163540.31981-1-chris@chris-wilson.co.uk>

On Fri, Mar 24, 2017 at 04:35:38PM +0000, Chris Wilson wrote:
> Note all of our target platforms have clflush. For those without, just
> assume the status page is sufficiently coherent that we do not need our
> paranoia.
> 
> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Fixes: 14a6bbf9e535 ("drm/i915: Replace irq_seqno_barrier on hws write with a clflush")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 22 +++++++++++++++-------
>  1 file changed, 15 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 2ecb41788fb6..b5ce6692ed8a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -454,14 +454,22 @@ intel_read_status_page(struct intel_engine_cs *engine, int reg)
>  }
>  
>  static inline void
> -intel_write_status_page(struct intel_engine_cs *engine,
> -			int reg, u32 value)
> +intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
>  {
> -	mb();
> -	clflush(&engine->status_page.page_addr[reg]);
> -	engine->status_page.page_addr[reg] = value;
> -	clflush(&engine->status_page.page_addr[reg]);
> -	mb();
> +	/* Writing into the status page should be done sparingly. Since
> +	 * we do when we are uncertain of the device state, we take a bit
> +	 * if extra paranoia to try and ensure that the HWS takes the value
> +	 * we give and that it doesn't end up trapped inside the CPU!
> +	 */
> +	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
> +		mb();
> +		clflush(&engine->status_page.page_addr[reg]);
> +		engine->status_page.page_addr[reg] = value;
> +		clflush(&engine->status_page.page_addr[reg]);
> +		mb();
> +	} else {
> +		WRITE_ONCE(engine->status_page.page_addr[reg], value);
> +	}

Fixes the illegal opcode explosion.
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Unfortunately the GPU still dies as soon as I fire up glxgears. 4.9
seems to be working just fine, so looks like a kernel regression.

>  }
>  
>  /*
> -- 
> 2.11.0

-- 
Ville Syrjälä
Intel OTC
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  parent reply	other threads:[~2017-03-24 19:05 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-24 16:35 [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush Chris Wilson
2017-03-24 16:35 ` [PATCH 2/3] drm/i915: Remove unused intel_flush_status_page() Chris Wilson
2017-03-27 10:09   ` Joonas Lahtinen
2017-03-24 16:35 ` [PATCH 3/3] drm/i915: Use BIT() for computing the engine's flag Chris Wilson
2017-03-27 10:08   ` Joonas Lahtinen
2017-03-24 16:46 ` [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush Chris Wilson
2017-03-24 16:53 ` ✓ Fi.CI.BAT: success for series starting with [1/3] " Patchwork
2017-03-27 12:19   ` Chris Wilson
2017-03-24 19:05 ` Ville Syrjälä [this message]
2017-03-24 20:53   ` [PATCH 1/3] " Ville Syrjälä
2017-03-24 21:04     ` Chris Wilson
2017-03-24 21:12       ` Ville Syrjälä
2017-03-27 11:50 ` Mika Kuoppala

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