All of lore.kernel.org
 help / color / mirror / Atom feed
From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v3 1/8] ppc/xics: introduce an 'icp' backlink under PowerPCCPU
Date: Wed, 29 Mar 2017 15:11:52 +1100	[thread overview]
Message-ID: <20170329041152.GV21068@umbus.fritz.box> (raw)
In-Reply-To: <1490686352-24017-2-git-send-email-clg@kaod.org>

[-- Attachment #1: Type: text/plain, Size: 6461 bytes --]

On Tue, Mar 28, 2017 at 09:32:25AM +0200, Cédric Le Goater wrote:
> Today, the ICPState array of the sPAPR machine is indexed with
> 'cpu_index' of the CPUState. This numbering of CPUs is internal to
> QEMU and the guest only knows about what is exposed in the device
> tree, that is the 'cpu_dt_id'. This is why sPAPR uses the helper
> xics_get_cpu_index_by_dt_id() to do the mapping in a couple of places.
> 
> To provide a more generic XICS layer, we need to abstract the IRQ
> 'server' number and remove any assumption made on its nature. It
> should not be used as a 'cpu_index' for lookups like xics_cpu_setup()
> and xics_cpu_destroy() do.
> 
> To reach that goal, we choose to introduce an 'icp' backlink under
> PowerPCCPU, and let the machine core init routine do the ICPState
> lookup. The resulting object is stored under PowerPCCPU which is
> passed on to xics_cpu_setup(). The IRQ 'server' number in XICS is now
> generic. sPAPR uses 'cpu_dt_id' and PowerNV will use 'PIR' number.
> 
> This also has the benefit of simplifying the sPAPR hcall routines
> which do not need to do any ICPState lookups anymore.

Since you've changed the type to a generic Object *, the name needs to
be changed to something generic as well.  Maybe 'intc' or
'irq_private'.

> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> 
> Changes since v2:
> 
>  - changed the 'icp' backlink type to be an 'Object'
> 
>  hw/intc/xics.c          |  4 ++--
>  hw/intc/xics_spapr.c    | 20 +++++---------------
>  hw/ppc/spapr_cpu_core.c |  5 ++++-
>  target/ppc/cpu.h        |  1 +
>  4 files changed, 12 insertions(+), 18 deletions(-)
> 
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index e740989a1162..bb485cc5b078 100644
> --- a/hw/intc/xics.c
> +++ b/hw/intc/xics.c
> @@ -52,7 +52,7 @@ int xics_get_cpu_index_by_dt_id(int cpu_dt_id)
>  void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu)
>  {
>      CPUState *cs = CPU(cpu);
> -    ICPState *icp = xics_icp_get(xi, cs->cpu_index);
> +    ICPState *icp = ICP(cpu->icp);
>  
>      assert(icp);
>      assert(cs == icp->cs);
> @@ -65,7 +65,7 @@ void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu)
>  {
>      CPUState *cs = CPU(cpu);
>      CPUPPCState *env = &cpu->env;
> -    ICPState *icp = xics_icp_get(xi, cs->cpu_index);
> +    ICPState *icp = ICP(cpu->icp);
>      ICPStateClass *icpc;
>  
>      assert(icp);
> diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
> index 84d24b2837a7..6144f9876ae3 100644
> --- a/hw/intc/xics_spapr.c
> +++ b/hw/intc/xics_spapr.c
> @@ -43,11 +43,9 @@
>  static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>                             target_ulong opcode, target_ulong *args)
>  {
> -    CPUState *cs = CPU(cpu);
> -    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index);
>      target_ulong cppr = args[0];
>  
> -    icp_set_cppr(icp, cppr);
> +    icp_set_cppr(ICP(cpu->icp), cppr);
>      return H_SUCCESS;
>  }
>  
> @@ -69,9 +67,7 @@ static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>  static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>                             target_ulong opcode, target_ulong *args)
>  {
> -    CPUState *cs = CPU(cpu);
> -    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index);
> -    uint32_t xirr = icp_accept(icp);
> +    uint32_t xirr = icp_accept(ICP(cpu->icp));
>  
>      args[0] = xirr;
>      return H_SUCCESS;
> @@ -80,9 +76,7 @@ static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>  static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>                               target_ulong opcode, target_ulong *args)
>  {
> -    CPUState *cs = CPU(cpu);
> -    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index);
> -    uint32_t xirr = icp_accept(icp);
> +    uint32_t xirr = icp_accept(ICP(cpu->icp));
>  
>      args[0] = xirr;
>      args[1] = cpu_get_host_ticks();
> @@ -92,21 +86,17 @@ static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>  static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>                            target_ulong opcode, target_ulong *args)
>  {
> -    CPUState *cs = CPU(cpu);
> -    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index);
>      target_ulong xirr = args[0];
>  
> -    icp_eoi(icp, xirr);
> +    icp_eoi(ICP(cpu->icp), xirr);
>      return H_SUCCESS;
>  }
>  
>  static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>                              target_ulong opcode, target_ulong *args)
>  {
> -    CPUState *cs = CPU(cpu);
> -    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index);
>      uint32_t mfrr;
> -    uint32_t xirr = icp_ipoll(icp, &mfrr);
> +    uint32_t xirr = icp_ipoll(ICP(cpu->icp), &mfrr);
>  
>      args[0] = xirr;
>      args[1] = mfrr;
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> index 6883f0991ae9..f9ca3f09a0f8 100644
> --- a/hw/ppc/spapr_cpu_core.c
> +++ b/hw/ppc/spapr_cpu_core.c
> @@ -63,6 +63,8 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
>                             Error **errp)
>  {
>      CPUPPCState *env = &cpu->env;
> +    XICSFabric *xi = XICS_FABRIC(spapr);
> +    ICPState *icp = xics_icp_get(xi, CPU(cpu)->cpu_index);
>  
>      /* Set time-base frequency to 512 MHz */
>      cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
> @@ -80,7 +82,8 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
>          }
>      }
>  
> -    xics_cpu_setup(XICS_FABRIC(spapr), cpu);
> +    cpu->icp = OBJECT(icp);
> +    xics_cpu_setup(xi, cpu);
>  
>      qemu_register_reset(spapr_cpu_reset, cpu);
>      spapr_cpu_reset(cpu);
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 5ee33b3fd315..774f2d717831 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1196,6 +1196,7 @@ struct PowerPCCPU {
>      uint32_t max_compat;
>      uint32_t compat_pvr;
>      PPCVirtualHypervisor *vhyp;
> +    Object *icp;
>  
>      /* Fields related to migration compatibility hacks */
>      bool pre_2_8_migration;

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

  reply	other threads:[~2017-03-29  4:34 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-28  7:32 [Qemu-devel] [PATCH v3 0/8] ppc/pnv: interrupt controller (POWER8) Cédric Le Goater
2017-03-28  7:32 ` [Qemu-devel] [PATCH v3 1/8] ppc/xics: introduce an 'icp' backlink under PowerPCCPU Cédric Le Goater
2017-03-29  4:11   ` David Gibson [this message]
2017-03-29  7:14     ` Cédric Le Goater
2017-03-30  1:26       ` David Gibson
2017-03-28  7:32 ` [Qemu-devel] [PATCH v3 2/8] spapr: move the IRQ server number mapping under the machine Cédric Le Goater
2017-03-28  7:32 ` [Qemu-devel] [PATCH v3 3/8] ppc/xics: add a realize() handler to ICPStateClass Cédric Le Goater
2017-03-28  7:32 ` [Qemu-devel] [PATCH v3 4/8] ppc/pnv: add a PnvICPState object Cédric Le Goater
2017-03-28  7:32 ` [Qemu-devel] [PATCH v3 5/8] ppc/pnv: create the ICP and ICS objects under the machine Cédric Le Goater
2017-03-29  5:18   ` David Gibson
2017-03-29  8:13     ` Cédric Le Goater
2017-03-30  1:55       ` David Gibson
2017-03-30  8:15         ` Cédric Le Goater
2017-04-02  6:11           ` David Gibson
2017-03-28  7:32 ` [Qemu-devel] [PATCH v3 6/8] ppc/pnv: add a helper to calculate MMIO addresses registers Cédric Le Goater
2017-03-28  7:32 ` [Qemu-devel] [PATCH v3 7/8] ppc/pnv: link the CPUs to the machine XICSFabric Cédric Le Goater
2017-03-29  5:20   ` David Gibson
2017-03-29  7:16     ` Cédric Le Goater
2017-03-28  7:32 ` [Qemu-devel] [PATCH v3 8/8] ppc/pnv: add memory regions for the ICP registers Cédric Le Goater

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20170329041152.GV21068@umbus.fritz.box \
    --to=david@gibson.dropbear.id.au \
    --cc=clg@kaod.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.