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From: Roger Pau Monne <roger.pau@citrix.com>
To: xen-devel@lists.xenproject.org, konrad.wilk@oracle.com,
	boris.ostrovsky@oracle.com
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
	Jan Beulich <jbeulich@suse.com>,
	Roger Pau Monne <roger.pau@citrix.com>
Subject: [PATCH v3 5/8] x86/vioapic: allow the vIO APIC to have a variable number of pins
Date: Wed, 29 Mar 2017 15:47:30 +0100	[thread overview]
Message-ID: <20170329144733.4709-4-roger.pau@citrix.com> (raw)
In-Reply-To: <20170329143918.4445-1-roger.pau@citrix.com>

Although it's still always set to VIOAPIC_NUM_PINS (48).

Add a new field to the hvm_ioapic struct to contain the number of pins (number
of IO redirection table entries) and turn the redirection table into a variable
sized array.

Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
---
Cc: Jan Beulich <jbeulich@suse.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
---
Changes since v2:
 - Undefine VIOAPIC_NUM_PINS for hypervisor code.

Changes since v1:
 - Almost completely reworked due to previous changes.
---
 xen/arch/x86/hvm/vioapic.c             | 23 ++++++++++++++++-------
 xen/include/asm-x86/hvm/vioapic.h      |  4 +++-
 xen/include/public/arch-x86/hvm/save.h |  2 ++
 3 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c
index 3e92947abf..6bc8dbdd42 100644
--- a/xen/arch/x86/hvm/vioapic.c
+++ b/xen/arch/x86/hvm/vioapic.c
@@ -53,7 +53,7 @@ static uint32_t vioapic_read_indirect(const struct hvm_vioapic *vioapic)
     case VIOAPIC_REG_VERSION:
         result = ((union IO_APIC_reg_01){
                   .bits = { .version = VIOAPIC_VERSION_ID,
-                            .entries = VIOAPIC_NUM_PINS - 1 }
+                            .entries = vioapic->nr_pins - 1 }
                   }).raw;
         break;
 
@@ -73,7 +73,7 @@ static uint32_t vioapic_read_indirect(const struct hvm_vioapic *vioapic)
         uint32_t redir_index = (vioapic->ioregsel - VIOAPIC_REG_RTE0) >> 1;
         uint64_t redir_content;
 
-        if ( redir_index >= VIOAPIC_NUM_PINS )
+        if ( redir_index >= vioapic->nr_pins )
         {
             gdprintk(XENLOG_WARNING, "apic_mem_readl:undefined ioregsel %x\n",
                      vioapic->ioregsel);
@@ -197,7 +197,7 @@ static void vioapic_write_indirect(
         HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "rte[%02x].%s = %08x",
                     redir_index, vioapic->ioregsel & 1 ? "hi" : "lo", val);
 
-        if ( redir_index >= VIOAPIC_NUM_PINS )
+        if ( redir_index >= vioapic->nr_pins )
         {
             gdprintk(XENLOG_WARNING, "vioapic_write_indirect "
                      "error register %x\n", vioapic->ioregsel);
@@ -368,7 +368,7 @@ void vioapic_irq_positive_edge(struct domain *d, unsigned int irq)
 
     HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "irq %x", irq);
 
-    ASSERT(irq < VIOAPIC_NUM_PINS);
+    ASSERT(irq < vioapic->nr_pins);
     ASSERT(spin_is_locked(&d->arch.hvm_domain.irq_lock));
 
     ent = &vioapic->redirtbl[irq];
@@ -397,7 +397,7 @@ void vioapic_update_EOI(struct domain *d, u8 vector)
 
     spin_lock(&d->arch.hvm_domain.irq_lock);
 
-    for ( gsi = 0; gsi < VIOAPIC_NUM_PINS; gsi++ )
+    for ( gsi = 0; gsi < vioapic->nr_pins; gsi++ )
     {
         ent = &vioapic->redirtbl[gsi];
         if ( ent->fields.vector != vector )
@@ -431,6 +431,9 @@ static int ioapic_save(struct domain *d, hvm_domain_context_t *h)
     if ( !has_vioapic(d) )
         return 0;
 
+    if ( s->nr_pins != ARRAY_SIZE(s->domU.redirtbl) )
+        return -EOPNOTSUPP;
+
     return hvm_save_entry(IOAPIC, 0, h, &s->domU);
 }
 
@@ -441,6 +444,9 @@ static int ioapic_load(struct domain *d, hvm_domain_context_t *h)
     if ( !has_vioapic(d) )
         return -ENODEV;
 
+    if ( s->nr_pins != ARRAY_SIZE(s->domU.redirtbl) )
+        return -EOPNOTSUPP;
+
     return hvm_load_entry(IOAPIC, h, &s->domU);
 }
 
@@ -449,14 +455,16 @@ HVM_REGISTER_SAVE_RESTORE(IOAPIC, ioapic_save, ioapic_load, 1, HVMSR_PER_DOM);
 void vioapic_reset(struct domain *d)
 {
     struct hvm_vioapic *vioapic = domain_vioapic(d);
+    uint32_t nr_pins = vioapic->nr_pins;
     int i;
 
     if ( !has_vioapic(d) )
         return;
 
-    memset(vioapic, 0, sizeof(*vioapic));
+    memset(vioapic, 0, hvm_vioapic_size(nr_pins));
     vioapic->domain = d;
-    for ( i = 0; i < VIOAPIC_NUM_PINS; i++ )
+    vioapic->nr_pins = nr_pins;
+    for ( i = 0; i < nr_pins; i++ )
         vioapic->redirtbl[i].fields.mask = 1;
     vioapic->base_address = VIOAPIC_DEFAULT_BASE_ADDRESS;
 }
@@ -471,6 +479,7 @@ int vioapic_init(struct domain *d)
         return -ENOMEM;
 
     d->arch.hvm_domain.vioapic->domain = d;
+    domain_vioapic(d)->nr_pins = ARRAY_SIZE(domain_vioapic(d)->domU.redirtbl);
     vioapic_reset(d);
 
     register_mmio_handler(d, &vioapic_mmio_ops);
diff --git a/xen/include/asm-x86/hvm/vioapic.h b/xen/include/asm-x86/hvm/vioapic.h
index ab7be9e741..711f294fbe 100644
--- a/xen/include/asm-x86/hvm/vioapic.h
+++ b/xen/include/asm-x86/hvm/vioapic.h
@@ -49,12 +49,14 @@
 
 struct hvm_vioapic {
     struct domain *domain;
+    uint32_t nr_pins;
     union {
-        XEN_HVM_VIOAPIC(, VIOAPIC_NUM_PINS);
+        XEN_HVM_VIOAPIC(, 0);
         struct hvm_hw_vioapic domU;
     };
 };
 
+#define hvm_vioapic_size(cnt) offsetof(struct hvm_vioapic, redirtbl[cnt])
 #define domain_vioapic(d) ((d)->arch.hvm_domain.vioapic)
 #define vioapic_domain(v) ((v)->domain)
 
diff --git a/xen/include/public/arch-x86/hvm/save.h b/xen/include/public/arch-x86/hvm/save.h
index ab848f6467..816973b9c2 100644
--- a/xen/include/public/arch-x86/hvm/save.h
+++ b/xen/include/public/arch-x86/hvm/save.h
@@ -393,6 +393,8 @@ XEN_HVM_VIOAPIC(hvm_hw_vioapic, VIOAPIC_NUM_PINS);
 
 #ifndef __XEN__
 #undef XEN_HVM_VIOAPIC
+#else
+#undef VIOAPIC_NUM_PINS
 #endif
 
 DECLARE_HVM_SAVE_TYPE(IOAPIC, 4, struct hvm_hw_vioapic);
-- 
2.11.0 (Apple Git-81)


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  parent reply	other threads:[~2017-03-29 14:48 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-29 14:39 [PATCH v3 0/8] x86/vioapic: introduce support for multiple vIO APICs Roger Pau Monne
2017-03-29 14:39 ` [PATCH v3 1/8] x86/vioapic: expand hvm_vioapic to contain vIO APIC internal state Roger Pau Monne
2017-03-31 14:52   ` Jan Beulich
2017-03-29 14:47 ` [PATCH v3 2/8] x86/hvm: introduce hvm_domain_irq macro Roger Pau Monne
2017-03-31  5:10   ` Tian, Kevin
2017-03-31 14:53   ` Jan Beulich
2017-03-29 14:47 ` [PATCH v3 3/8] x86/irq: rename NR_HVM_IRQS and break it's dependency on VIOAPIC_NUM_PINS Roger Pau Monne
2017-03-31 15:01   ` Jan Beulich
2017-04-04 10:15     ` Roger Pau Monne
2017-04-04 10:18       ` Jan Beulich
2017-03-29 14:47 ` [PATCH v3 4/8] x86/hvm: convert gsi_assert_count into a variable size array Roger Pau Monne
2017-03-31 15:16   ` Jan Beulich
2017-04-03 16:18     ` Roger Pau Monne
2017-03-29 14:47 ` Roger Pau Monne [this message]
2017-03-31 15:20   ` [PATCH v3 5/8] x86/vioapic: allow the vIO APIC to have a variable number of pins Jan Beulich
2017-03-29 14:47 ` [PATCH v3 6/8] x86/vioapic: introduce support for multiple vIO APICS Roger Pau Monne
2017-03-31 15:48   ` Jan Beulich
2017-03-29 14:47 ` [PATCH v3 7/8] x86/ioapic: add prototype for io_apic_gsi_base to io_apic.h Roger Pau Monne
2017-03-29 14:47 ` [PATCH v3 8/8] x86/vioapic: allow PVHv2 Dom0 to have more than one IO APIC Roger Pau Monne
2017-03-30  8:16 ` [PATCH v3 0/8] x86/vioapic: introduce support for multiple vIO APICs Roger Pau Monne

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