From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/4] drm/i915: Wait for inflight writes before checking intel_engine_is_idle()
Date: Wed, 29 Mar 2017 22:36:16 +0100 [thread overview]
Message-ID: <20170329213619.19122-1-chris@chris-wilson.co.uk> (raw)
Some GPUs may have writes inflight much longer than expected, so before
declaring the GPU is idle, try to flush them using any
engine->irq_seqno_barrier() if available. By allowing them to be
flushed, we can be a little more confident that the GPU really is idle
when we think it is!
References: https://bugs.freedesktop.org/show_bug.cgi?id=98836
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index c76a64483d64..ff6d0e1d1306 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1074,6 +1074,10 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+ /* We have to allow time for writes to land from the GPU. */
+ if (engine->irq_seqno_barrier)
+ engine->irq_seqno_barrier(engine);
+
/* Any inflight/incomplete requests? */
if (!i915_seqno_passed(intel_engine_get_seqno(engine),
intel_engine_last_submit(engine)))
--
2.11.0
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next reply other threads:[~2017-03-29 21:36 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-29 21:36 Chris Wilson [this message]
2017-03-29 21:36 ` [PATCH 2/4] drm/i915: Wait for all engines to be idle as part of i915_gem_wait_for_idle() Chris Wilson
2017-03-29 22:05 ` Chris Wilson
2017-03-29 22:18 ` Chris Wilson
2017-03-29 21:36 ` [PATCH 3/4] drm/i915: Remove redudant wait for each engine to idle from seqno wrap Chris Wilson
2017-03-29 21:36 ` [PATCH 4/4] drm/i915: Combine reset_all_global_seqno() loops into one Chris Wilson
2017-03-29 21:40 ` [PATCH] " Chris Wilson
2017-03-29 21:39 ` ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Wait for inflight writes before checking intel_engine_is_idle() Patchwork
2017-03-29 22:00 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Wait for inflight writes before checking intel_engine_is_idle() (rev2) Patchwork
2017-03-29 23:28 ` [PATCH 1/4] drm/i915: Wait for inflight writes before checking intel_engine_is_idle() Chris Wilson
2017-03-30 8:29 ` Mika Kuoppala
2017-03-30 8:40 ` Chris Wilson
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