[PATCH v2 00/16] DC Patches Apr 3, 2017

[PATCH v2 00/16] DC Patches Apr 3, 2017

[Harry Wentland]

* First phase of getting multi-plane support
* Using DRM for all aux/i2c & edid read
* Fix screen flicker on Tonga & Bonaire
* Bunch of Raven bandwidth fixes
* Bunch of other fixes

v2: Forgot to remove ddc_service module. This is no longer
    needed. Please disregard previous patch set.


Amy Zhang (1):
  drm/amd/display: PSR Aux Channel and Static Screen Support Fix

Andrey Grodzovsky (5):
  drm/amd/display: Remove get_connector_for_link.
  drm/amd/display: Remove get_connector_for_sink.
  drm/amd/display: Fix i2c write flag.
  drm/amd/display: Refactor edid read.
  drm/amd/display: Fix s3 hang on resume.

Dmytro Laktyushkin (1):
  drm/amd/display: fix dce_calc surface pitch setting for non underlay
    pipes

Harry Wentland (1):
  drm/amd/display: Fix cleanup in amdgpu_dm_initialize_drm_device

Jordan Lazare (2):
  drm/amd/display: Fill in vrefresh and min_vblank_time for dce8/dce10
  drm/amd/display: Log clock source in error condition

Reza Amini (2):
  drm/amd/display: remove surface validation against stream rect
  drm/amd/display: refactor member referencing to improve readability

Shirish S (2):
  drm/amd/display: decouple per-crtc-plane model
  drm/amd/display: update plane functionalities

Yongqiang Sun (1):
  drm/amd/display: Ignore visible flag when check surface update type.

Zeyu Fan (1):
  drm/amd/display: Temporary disable PSR for HBR2 & HBR3

 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h           |  21 ++
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |  76 +++--
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c  | 112 +++----
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c  |  16 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h  |   2 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c    |  54 +++-
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.h    |   2 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 139 +++++++--
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h    |   5 +-
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c   |   4 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c           |  80 +++--
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      |  55 +---
 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c  | 337 +--------------------
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   |  33 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 107 +++----
 drivers/gpu/drm/amd/display/dc/dc.h                |  25 +-
 drivers/gpu/drm/amd/display/dc/dc_types.h          |   6 +
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c     |   3 +-
 .../amd/display/dc/dce100/dce100_hw_sequencer.c    |  21 ++
 .../amd/display/dc/dce100/dce100_hw_sequencer.h    |   5 +
 .../drm/amd/display/dc/dce100/dce100_resource.c    |   7 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |   8 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.h    |   8 +
 .../drm/amd/display/dc/dce110/dce110_resource.c    |   7 +-
 .../drm/amd/display/dc/dce112/dce112_resource.c    |   7 +-
 .../drm/amd/display/dc/dce120/dce120_resource.c    |   2 +
 .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c  |   2 +
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  |   7 +-
 drivers/gpu/drm/amd/display/dc/dm_helpers.h        |  10 +
 drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c     |   9 +-
 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h   |  38 ++-
 .../drm/amd/display/include/ddc_service_types.h    |  28 --
 .../gpu/drm/amd/display/include/i2caux_interface.h |   3 +
 33 files changed, 564 insertions(+), 675 deletions(-)

-- 
2.11.0

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[PATCH v2 01/16] drm/amd/display: decouple per-crtc-plane model

[Harry Wentland]

From: Shirish S <shirish.s@amd.com>

Current design has per-crtc-plane model.
As a result, for asic's that support underlay,
are unable to expose it to user space for modesetting.

To enable this, the drm driver intialisation now runs
for number of surfaces instead of stream/crtc.

This patch plumbs surface capabilities to drm framework
so that it can be effectively used by user space.

Tests: (On Chromium OS for Stoney Only)
* 'modetest -p'  now shows additional plane
  with YUV capabilities in case of CZ and ST.
* 'plane_test' fails with below error:
  [drm:amdgpu_dm_connector_atomic_set_property [amdgpu]] *ERROR* Unsupported screen depth 0
  as ther is no support for YUYV
* Checked multimonitor display works fine

Change-Id: Ibc112d1c7f76539b530b4e11862bb57f2e480121
Signed-off-by: Shirish S <shirish.s@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h           |  8 +++
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 67 ++++++++++++++-----
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 75 +++++++++++++++-------
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h    |  5 +-
 drivers/gpu/drm/amd/display/dc/dc.h                |  1 +
 .../drm/amd/display/dc/dce100/dce100_resource.c    |  2 +
 .../drm/amd/display/dc/dce110/dce110_resource.c    |  2 +
 .../drm/amd/display/dc/dce112/dce112_resource.c    |  2 +
 .../drm/amd/display/dc/dce120/dce120_resource.c    |  2 +
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  |  2 +
 10 files changed, 127 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 31484125e875..da3b12599019 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -59,6 +59,7 @@ struct amdgpu_hpd;
 
 #define AMDGPU_MAX_HPD_PINS 6
 #define AMDGPU_MAX_CRTCS 6
+#define AMDGPU_MAX_PLANES 6
 #define AMDGPU_MAX_AFMT_BLOCKS 9
 
 enum amdgpu_rmx_type {
@@ -338,6 +339,7 @@ struct amdgpu_mode_info {
 	struct card_info *atom_card_info;
 	bool mode_config_initialized;
 	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
+	struct amdgpu_plane *planes[AMDGPU_MAX_PLANES];
 	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
 	/* DVI-I properties */
 	struct drm_property *coherent_mode_property;
@@ -371,6 +373,7 @@ struct amdgpu_mode_info {
 	int			num_dig; /* number of dig blocks */
 	int			disp_priority;
 	const struct amdgpu_display_funcs *funcs;
+	enum drm_plane_type *plane_type;
 };
 
 #define AMDGPU_MAX_BL_LEVEL 0xFF
@@ -452,6 +455,11 @@ struct amdgpu_crtc {
 	struct drm_pending_vblank_event *event;
 };
 
+struct amdgpu_plane {
+	struct drm_plane base;
+	enum drm_plane_type plane_type;
+};
+
 struct amdgpu_encoder_atom_dig {
 	bool linkb;
 	/* atom dig */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ed7ca675ff37..18635954f9fd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -55,6 +55,28 @@
 
 #include "modules/inc/mod_freesync.h"
 
+static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = {
+	DRM_PLANE_TYPE_PRIMARY,
+	DRM_PLANE_TYPE_PRIMARY,
+	DRM_PLANE_TYPE_PRIMARY,
+	DRM_PLANE_TYPE_PRIMARY,
+	DRM_PLANE_TYPE_PRIMARY,
+	DRM_PLANE_TYPE_PRIMARY,
+};
+
+static enum drm_plane_type dm_surfaces_type_carizzo[AMDGPU_MAX_PLANES] = {
+	DRM_PLANE_TYPE_PRIMARY,
+	DRM_PLANE_TYPE_PRIMARY,
+	DRM_PLANE_TYPE_PRIMARY,
+	DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
+};
+
+static enum drm_plane_type dm_surfaces_type_stoney[AMDGPU_MAX_PLANES] = {
+	DRM_PLANE_TYPE_PRIMARY,
+	DRM_PLANE_TYPE_PRIMARY,
+	DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
+};
+
 /*
  * dm_vblank_get_counter
  *
@@ -1057,30 +1079,34 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 	uint32_t i;
 	struct amdgpu_connector *aconnector;
 	struct amdgpu_encoder *aencoder;
-	struct amdgpu_crtc *acrtc;
+	struct amdgpu_mode_info *mode_info = &adev->mode_info;
 	uint32_t link_cnt;
 
 	link_cnt = dm->dc->caps.max_links;
-
 	if (amdgpu_dm_mode_config_init(dm->adev)) {
 		DRM_ERROR("DM: Failed to initialize mode config\n");
-		return -1;
+		goto fail;
 	}
 
-	for (i = 0; i < dm->dc->caps.max_streams; i++) {
-		acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
-		if (!acrtc)
-			goto fail;
+	for (i = 0; i < dm->dc->caps.max_surfaces; i++) {
+		mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane),
+								 GFP_KERNEL);
+		if (!mode_info->planes[i]) {
+			DRM_ERROR("KMS: Failed to allocate surface\n");
+			goto fail_free_planes;
+		}
+		mode_info->planes[i]->plane_type = mode_info->plane_type[i];
+		if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 1)) {
+			DRM_ERROR("KMS: Failed to initialize plane\n");
+			goto fail_free_planes;
+		}
+	}
 
-		if (amdgpu_dm_crtc_init(
-			dm,
-			acrtc,
-			i)) {
+	for (i = 0; i < dm->dc->caps.max_streams; i++)
+		if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
 			DRM_ERROR("KMS: Failed to initialize crtc\n");
-			kfree(acrtc);
-			goto fail;
+			goto fail_free_planes;
 		}
-	}
 
 	dm->display_indexes_num = dm->dc->caps.max_streams;
 
@@ -1131,12 +1157,12 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 	case CHIP_VEGA10:
 		if (dce110_register_irq_handlers(dm->adev)) {
 			DRM_ERROR("DM: Failed to initialize IRQ\n");
-			return -1;
+			goto fail_free_encoder;
 		}
 		break;
 	default:
 		DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
-		return -1;
+		goto fail_free_encoder;
 	}
 
 	drm_mode_config_reset(dm->ddev);
@@ -1146,6 +1172,9 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 	kfree(aencoder);
 fail_free_connector:
 	kfree(aconnector);
+fail_free_planes:
+	for (i = 0; i < dm->dc->caps.max_surfaces; i++)
+		kfree(mode_info->planes[i]);
 fail:
 	return -1;
 }
@@ -1537,6 +1566,7 @@ static int dm_early_init(void *handle)
 		adev->mode_info.num_crtc = 6;
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 6;
+		adev->mode_info.plane_type = dm_surfaces_type_default;
 #ifdef CONFIG_DRM_AMDGPU_CIK
 		if (adev->mode_info.funcs == NULL)
 			adev->mode_info.funcs = &dm_dce_v8_0_display_funcs;
@@ -1547,6 +1577,7 @@ static int dm_early_init(void *handle)
 		adev->mode_info.num_crtc = 6;
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 7;
+		adev->mode_info.plane_type = dm_surfaces_type_default;
 		if (adev->mode_info.funcs == NULL)
 			adev->mode_info.funcs = &dm_dce_v10_0_display_funcs;
 		break;
@@ -1554,6 +1585,7 @@ static int dm_early_init(void *handle)
 		adev->mode_info.num_crtc = 3;
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 9;
+		adev->mode_info.plane_type = dm_surfaces_type_carizzo;
 		if (adev->mode_info.funcs == NULL)
 			adev->mode_info.funcs = &dm_dce_v11_0_display_funcs;
 		break;
@@ -1561,6 +1593,7 @@ static int dm_early_init(void *handle)
 		adev->mode_info.num_crtc = 2;
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 9;
+		adev->mode_info.plane_type = dm_surfaces_type_stoney;
 		if (adev->mode_info.funcs == NULL)
 			adev->mode_info.funcs = &dm_dce_v11_0_display_funcs;
 		break;
@@ -1569,6 +1602,7 @@ static int dm_early_init(void *handle)
 		adev->mode_info.num_crtc = 5;
 		adev->mode_info.num_hpd = 5;
 		adev->mode_info.num_dig = 5;
+		adev->mode_info.plane_type = dm_surfaces_type_default;
 		if (adev->mode_info.funcs == NULL)
 			adev->mode_info.funcs = &dm_dce_v11_0_display_funcs;
 		break;
@@ -1576,6 +1610,7 @@ static int dm_early_init(void *handle)
 		adev->mode_info.num_crtc = 6;
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 6;
+		adev->mode_info.plane_type = dm_surfaces_type_default;
 		if (adev->mode_info.funcs == NULL)
 			adev->mode_info.funcs = &dm_dce_v11_0_display_funcs;
 		break;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 929a4c8ea62d..2655da303cf8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1610,6 +1610,8 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
 };
 
 static const struct drm_plane_funcs dm_plane_funcs = {
+	.update_plane   = drm_atomic_helper_update_plane,
+	.disable_plane  = drm_atomic_helper_disable_plane,
 	.reset = drm_atomic_helper_plane_reset,
 	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state
@@ -1741,37 +1743,67 @@ static uint32_t rgb_formats[] = {
 	DRM_FORMAT_ABGR2101010,
 };
 
-int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
-			struct amdgpu_crtc *acrtc,
-			uint32_t crtc_index)
+static uint32_t yuv_formats[] = {
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+};
+
+int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
+			struct amdgpu_plane *aplane,
+			unsigned long possible_crtcs)
 {
-	int res = -ENOMEM;
+	int res = -EPERM;
 
-	struct drm_plane *primary_plane =
-		kzalloc(sizeof(*primary_plane), GFP_KERNEL);
+	switch (aplane->plane_type) {
+	case DRM_PLANE_TYPE_PRIMARY:
+		aplane->base.format_default = true;
 
-	if (!primary_plane)
-		goto fail_plane;
+		res = drm_universal_plane_init(
+				dm->adev->ddev,
+				&aplane->base,
+				possible_crtcs,
+				&dm_plane_funcs,
+				rgb_formats,
+				ARRAY_SIZE(rgb_formats),
+				aplane->plane_type, NULL);
+		break;
+	case DRM_PLANE_TYPE_OVERLAY:
+		res = drm_universal_plane_init(
+				dm->adev->ddev,
+				&aplane->base,
+				possible_crtcs,
+				&dm_plane_funcs,
+				yuv_formats,
+				ARRAY_SIZE(yuv_formats),
+				aplane->plane_type, NULL);
+		break;
+	case DRM_PLANE_TYPE_CURSOR:
+		DRM_ERROR("KMS: Cursor plane not implemented.");
+		break;
+	}
 
-	primary_plane->format_default = true;
+	drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
 
-	res = drm_universal_plane_init(
-		dm->adev->ddev,
-		primary_plane,
-		0,
-		&dm_plane_funcs,
-		rgb_formats,
-		ARRAY_SIZE(rgb_formats),
-		DRM_PLANE_TYPE_PRIMARY, NULL);
+	return res;
+}
 
-	primary_plane->crtc = &acrtc->base;
+int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
+			struct drm_plane *plane,
+			uint32_t crtc_index)
+{
+	struct amdgpu_crtc *acrtc;
+	int res = -ENOMEM;
 
-	drm_plane_helper_add(primary_plane, &dm_plane_helper_funcs);
+	acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
+	if (!acrtc)
+		goto fail;
 
 	res = drm_crtc_init_with_planes(
 			dm->ddev,
 			&acrtc->base,
-			primary_plane,
+			plane,
 			NULL,
 			&amdgpu_dm_crtc_funcs, NULL);
 
@@ -1791,8 +1823,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 
 	return 0;
 fail:
-	kfree(primary_plane);
-fail_plane:
+	kfree(acrtc);
 	acrtc->crtc_id = -1;
 	return res;
 }
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
index 1bbeb87dc9d0..ab6d51dbbf4b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
@@ -34,8 +34,11 @@ struct dc_validation_set;
 struct dc_surface;
 
 /*TODO Jodan Hersen use the one in amdgpu_dm*/
+int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
+			struct amdgpu_plane *aplane,
+			unsigned long possible_crtcs);
 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
-			struct amdgpu_crtc *amdgpu_crtc,
+			struct drm_plane *plane,
 			uint32_t link_index);
 int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 			struct amdgpu_connector *amdgpu_connector,
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 0731045f6084..9dd8b2ad4c59 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -45,6 +45,7 @@ struct dc_caps {
 	uint32_t max_links;
 	uint32_t max_audios;
 	uint32_t max_slave_planes;
+	uint32_t max_surfaces;
 	uint32_t max_downscale_ratio;
 	uint32_t i2c_speed_in_khz;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index b6f77f88be9c..d1685df09815 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -1035,6 +1035,8 @@ static bool construct(
 		}
 	}
 
+	dc->public.caps.max_surfaces =  pool->base.pipe_count;
+
 	if (!resource_construct(num_virtual_links, dc, &pool->base,
 			&res_create_funcs))
 		goto res_create_fail;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index e3002031c40d..065a2986b666 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1455,6 +1455,8 @@ static bool construct(
 	if (!dce110_hw_sequencer_construct(dc))
 		goto res_create_fail;
 
+	dc->public.caps.max_surfaces =  pool->base.pipe_count;
+
 	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);
 
 	bw_calcs_data_update_from_pplib(dc);
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 32aa1b5bf1f9..ece3ec72363d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1409,6 +1409,8 @@ static bool construct(
 			  &res_create_funcs))
 		goto res_create_fail;
 
+	dc->public.caps.max_surfaces =  pool->base.pipe_count;
+
 	/* Create hardware sequencer */
 	if (!dce112_hw_sequencer_construct(dc))
 		goto res_create_fail;
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index efa58889058b..f677a77ca6e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -1060,6 +1060,8 @@ static bool construct(
 	if (!dce120_hw_sequencer_create(dc))
 		goto controller_create_fail;
 
+	dc->public.caps.max_surfaces =  pool->base.pipe_count;
+
 	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);
 
 	bw_calcs_data_update_from_pplib(dc);
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index a3e8182885b2..752e0e7579b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -1043,6 +1043,8 @@ static bool construct(
 		}
 	}
 
+	dc->public.caps.max_surfaces =  pool->base.pipe_count;
+
 	if (!resource_construct(num_virtual_links, dc, &pool->base,
 			&res_create_funcs))
 		goto res_create_fail;
-- 
2.11.0

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[PATCH v2 02/16] drm/amd/display: Fix cleanup in amdgpu_dm_initialize_drm_device

[Harry Wentland]

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 18635954f9fd..b3a9a9058c4a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1077,15 +1077,15 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 {
 	struct amdgpu_display_manager *dm = &adev->dm;
 	uint32_t i;
-	struct amdgpu_connector *aconnector;
-	struct amdgpu_encoder *aencoder;
+	struct amdgpu_connector *aconnector = NULL;
+	struct amdgpu_encoder *aencoder = NULL;
 	struct amdgpu_mode_info *mode_info = &adev->mode_info;
 	uint32_t link_cnt;
 
 	link_cnt = dm->dc->caps.max_links;
 	if (amdgpu_dm_mode_config_init(dm->adev)) {
 		DRM_ERROR("DM: Failed to initialize mode config\n");
-		goto fail;
+		return -1;
 	}
 
 	for (i = 0; i < dm->dc->caps.max_surfaces; i++) {
@@ -1122,7 +1122,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 
 		aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
 		if (!aconnector)
-			goto fail;
+			goto fail_free_planes;
 
 		aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
 		if (!aencoder) {
@@ -1136,7 +1136,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 
 		if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
 			DRM_ERROR("KMS: Failed to initialize connector\n");
-			goto fail_free_connector;
+			goto fail_free_encoder;
 		}
 
 		if (dc_link_detect(dc_get_link_at_index(dm->dc, i), true))
@@ -1175,7 +1175,6 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 fail_free_planes:
 	for (i = 0; i < dm->dc->caps.max_surfaces; i++)
 		kfree(mode_info->planes[i]);
-fail:
 	return -1;
 }
 
-- 
2.11.0

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[PATCH v2 03/16] drm/amd/display: update plane functionalities

[Harry Wentland]

From: Shirish S <shirish.s@amd.com>

This patch introduces amdgpu_drm_plane_state
structure, which subclasses drm_plane_state and
holds data suitable for configuring hardware.

It switches reset(), atomic_duplicate_state()
& atomic_destroy_state() functions to new internal
implementation, earlier they were pointing to
drm core functions.

TESTS(On Chromium OS on Stoney Only)
* Builds without compilation errors.
* 'plane_test' passes for XR24 format
  based Overlay plane.
* Chromium OS ui comes up.

Change-Id: I62a353fd6d3e290d3b01e90f25699dc2392fa455
Signed-off-by: Shirish S <shirish.s@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h           | 13 +++++
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 55 ++++++++++++++++++++--
 2 files changed, 63 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index da3b12599019..be3e8d66955e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -56,6 +56,7 @@ struct amdgpu_hpd;
 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
+#define to_amdgpu_plane(x)	container_of(x, struct amdgpu_plane, base)
 
 #define AMDGPU_MAX_HPD_PINS 6
 #define AMDGPU_MAX_CRTCS 6
@@ -455,6 +456,18 @@ struct amdgpu_crtc {
 	struct drm_pending_vblank_event *event;
 };
 
+struct amdgpu_drm_plane_state {
+	struct drm_plane_state base;
+	unsigned int h_ratio;
+	unsigned int v_ratio;
+};
+
+static inline struct amdgpu_drm_plane_state *
+to_amdgpu_plane_state(struct drm_plane_state *state)
+{
+	return container_of(state, struct amdgpu_drm_plane_state, base);
+}
+
 struct amdgpu_plane {
 	struct drm_plane base;
 	enum drm_plane_type plane_type;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 2655da303cf8..0424b2d65793 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1609,12 +1609,57 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
 	.atomic_check = dm_encoder_helper_atomic_check
 };
 
+static void dm_drm_plane_reset(struct drm_plane *plane)
+{
+	struct amdgpu_drm_plane_state *amdgpu_state;
+
+	if (plane->state) {
+		amdgpu_state = to_amdgpu_plane_state(plane->state);
+		if (amdgpu_state->base.fb)
+			drm_framebuffer_unreference(amdgpu_state->base.fb);
+		kfree(amdgpu_state);
+		plane->state = NULL;
+	}
+
+	amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
+	if (amdgpu_state) {
+		plane->state = &amdgpu_state->base;
+		plane->state->plane = plane;
+	}
+}
+
+static struct drm_plane_state *
+dm_drm_plane_duplicate_state(struct drm_plane *plane)
+{
+	struct amdgpu_drm_plane_state *amdgpu_state;
+	struct amdgpu_drm_plane_state *copy;
+
+	amdgpu_state = to_amdgpu_plane_state(plane->state);
+	copy = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
+	if (!copy)
+		return NULL;
+
+	__drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
+	return &copy->base;
+}
+
+static void dm_drm_plane_destroy_state(struct drm_plane *plane,
+					   struct drm_plane_state *old_state)
+{
+	struct amdgpu_drm_plane_state *old_amdgpu_state =
+					to_amdgpu_plane_state(old_state);
+	__drm_atomic_helper_plane_destroy_state(old_state);
+	kfree(old_amdgpu_state);
+}
+
 static const struct drm_plane_funcs dm_plane_funcs = {
-	.update_plane   = drm_atomic_helper_update_plane,
-	.disable_plane  = drm_atomic_helper_disable_plane,
-	.reset = drm_atomic_helper_plane_reset,
-	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state
+	.update_plane	= drm_atomic_helper_update_plane,
+	.disable_plane	= drm_atomic_helper_disable_plane,
+	.destroy	= drm_plane_cleanup,
+	.set_property	= drm_atomic_helper_plane_set_property,
+	.reset = dm_drm_plane_reset,
+	.atomic_duplicate_state = dm_drm_plane_duplicate_state,
+	.atomic_destroy_state = dm_drm_plane_destroy_state,
 };
 
 static int dm_plane_helper_prepare_fb(
-- 
2.11.0

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[PATCH v2 04/16] drm/amd/display: remove surface validation against stream rect

[Harry Wentland]

From: Reza Amini <reza.amini@amd.com>

Surface information is by default copied from old context in dc_commit_stream.
Thus unchange streams will not be affected. For new streams, we shouldn't
validate the new mode against the surface configuration of old_context.

Change-Id: I401338f793fc1341d057ad2ffece2ea24c517e0e
Signed-off-by: Reza Amini <reza.amini@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 5 -----
 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 5 -----
 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 5 -----
 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c   | 5 -----
 4 files changed, 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index d1685df09815..7fae8537e18a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -788,11 +788,6 @@ static bool dce100_validate_surface_sets(
 		if (set[i].surface_count > 1)
 			return false;
 
-		if (set[i].surfaces[0]->clip_rect.width
-				< set[i].stream->src.width
-				|| set[i].surfaces[0]->clip_rect.height
-				< set[i].stream->src.height)
-			return false;
 		if (set[i].surfaces[0]->format
 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 			return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 065a2986b666..b4ab438e1c97 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1007,11 +1007,6 @@ static bool dce110_validate_surface_sets(
 		if (set[i].surface_count > 2)
 			return false;
 
-		if (set[i].surfaces[0]->clip_rect.width
-				> set[i].stream->src.width
-				|| set[i].surfaces[0]->clip_rect.height
-				> set[i].stream->src.height)
-			return false;
 		if (set[i].surfaces[0]->format
 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 			return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index ece3ec72363d..0a1ad2808129 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -972,11 +972,6 @@ static bool dce112_validate_surface_sets(
 		if (set[i].surface_count > 1)
 			return false;
 
-		if (set[i].surfaces[0]->clip_rect.width
-				> set[i].stream->src.width
-				|| set[i].surfaces[0]->clip_rect.height
-				> set[i].stream->src.height)
-			return false;
 		if (set[i].surfaces[0]->format
 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 			return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 752e0e7579b9..ab8cee3e734e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -804,11 +804,6 @@ static bool dce80_validate_surface_sets(
 		if (set[i].surface_count > 1)
 			return false;
 
-		if (set[i].surfaces[0]->clip_rect.width
-				> set[i].stream->src.width
-				|| set[i].surfaces[0]->clip_rect.height
-				> set[i].stream->src.height)
-			return false;
 		if (set[i].surfaces[0]->format
 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 			return false;
-- 
2.11.0

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[PATCH v2 05/16] drm/amd/display: refactor member referencing to improve readability

[Harry Wentland]

From: Reza Amini <reza.amini@amd.com>

Change-Id: I06f22e78a63e1ea251fcd847594fd2abaa8eda65
Signed-off-by: Reza Amini <reza.amini@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 107 ++++++++--------------
 1 file changed, 39 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 8f53d7a9f4dd..069f588a9e02 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1519,17 +1519,16 @@ static void set_avi_info_frame(
 	uint8_t cn0_cn1 = 0;
 	uint8_t *check_sum = NULL;
 	uint8_t byte_index = 0;
+	union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi;
 
 	color_space = pipe_ctx->stream->public.output_color_space;
 
 	/* Initialize header */
-	info_frame.avi_info_packet.info_packet_hdmi.bits.header.
-			info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
+	hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
 	/* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
 	* not be used in HDMI 2.0 (Section 10.1) */
-	info_frame.avi_info_packet.info_packet_hdmi.bits.header.version = 2;
-	info_frame.avi_info_packet.info_packet_hdmi.bits.header.length =
-			HDMI_AVI_INFOFRAME_SIZE;
+	hdmi_info->bits.header.version = 2;
+	hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
 
 	/*
 	 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
@@ -1555,52 +1554,41 @@ static void set_avi_info_frame(
 
 	/* Y0_Y1_Y2 : The pixel encoding */
 	/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
-	info_frame.avi_info_packet.info_packet_hdmi.bits.Y0_Y1_Y2 =
-		pixel_encoding;
+	hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding;
 
 	/* A0 = 1 Active Format Information valid */
-	info_frame.avi_info_packet.info_packet_hdmi.bits.A0 =
-		ACTIVE_FORMAT_VALID;
+	hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID;
 
 	/* B0, B1 = 3; Bar info data is valid */
-	info_frame.avi_info_packet.info_packet_hdmi.bits.B0_B1 =
-		BAR_INFO_BOTH_VALID;
+	hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID;
 
-	info_frame.avi_info_packet.info_packet_hdmi.bits.SC0_SC1 =
-			PICTURE_SCALING_UNIFORM;
+	hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
 
 	/* S0, S1 : Underscan / Overscan */
 	/* TODO: un-hardcode scan type */
 	scan_type = SCANNING_TYPE_UNDERSCAN;
-	info_frame.avi_info_packet.info_packet_hdmi.bits.S0_S1 = scan_type;
+	hdmi_info->bits.S0_S1 = scan_type;
 
 	/* C0, C1 : Colorimetry */
 	if (color_space == COLOR_SPACE_YCBCR709 ||
 			color_space == COLOR_SPACE_YCBCR709_LIMITED)
-		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
-				COLORIMETRY_ITU709;
+		hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
 	else if (color_space == COLOR_SPACE_YCBCR601 ||
 			color_space == COLOR_SPACE_YCBCR601_LIMITED)
-		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
-				COLORIMETRY_ITU601;
+		hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601;
 	else {
 		if (stream->public.timing.pixel_encoding != PIXEL_ENCODING_RGB)
 			BREAK_TO_DEBUGGER();
-		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
-				COLORIMETRY_NO_DATA;
+		hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA;
 	}
 	if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
 			color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
 			color_space == COLOR_SPACE_2020_YCBCR) {
-		info_frame.avi_info_packet.info_packet_hdmi.bits.EC0_EC2 =
-				COLORIMETRYEX_BT2020RGBYCBCR;
-		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
-				COLORIMETRY_EXTENDED;
+		hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
+		hdmi_info->bits.C0_C1   = COLORIMETRY_EXTENDED;
 	} else if (color_space == COLOR_SPACE_ADOBERGB) {
-		info_frame.avi_info_packet.info_packet_hdmi.bits.EC0_EC2 =
-				COLORIMETRYEX_ADOBERGB;
-		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
-				COLORIMETRY_EXTENDED;
+		hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
+		hdmi_info->bits.C0_C1   = COLORIMETRY_EXTENDED;
 	}
 
 	/* TODO: un-hardcode aspect ratio */
@@ -1609,93 +1597,76 @@ static void set_avi_info_frame(
 	switch (aspect) {
 	case ASPECT_RATIO_4_3:
 	case ASPECT_RATIO_16_9:
-		info_frame.avi_info_packet.info_packet_hdmi.bits.M0_M1 = aspect;
+		hdmi_info->bits.M0_M1 = aspect;
 		break;
 
 	case ASPECT_RATIO_NO_DATA:
 	case ASPECT_RATIO_64_27:
 	case ASPECT_RATIO_256_135:
 	default:
-		info_frame.avi_info_packet.info_packet_hdmi.bits.M0_M1 = 0;
+		hdmi_info->bits.M0_M1 = 0;
 	}
 
 	/* Active Format Aspect ratio - same as Picture Aspect Ratio. */
-	info_frame.avi_info_packet.info_packet_hdmi.bits.R0_R3 =
-			ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
+	hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
 
 	/* TODO: un-hardcode cn0_cn1 and itc */
 	cn0_cn1 = 0;
 	itc = false;
 
 	if (itc) {
-		info_frame.avi_info_packet.info_packet_hdmi.bits.ITC = 1;
-		info_frame.avi_info_packet.info_packet_hdmi.bits.CN0_CN1 =
-			cn0_cn1;
+		hdmi_info->bits.ITC     = 1;
+		hdmi_info->bits.CN0_CN1 = cn0_cn1;
 	}
 
 	/* TODO : We should handle YCC quantization */
 	/* but we do not have matrix calculation */
 	if (color_space == COLOR_SPACE_SRGB) {
-		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
-						RGB_QUANTIZATION_FULL_RANGE;
-		info_frame.avi_info_packet.info_packet_hdmi.bits.YQ0_YQ1 =
-						YYC_QUANTIZATION_FULL_RANGE;
+		hdmi_info->bits.Q0_Q1   = RGB_QUANTIZATION_FULL_RANGE;
+		hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
 	} else if (color_space == COLOR_SPACE_SRGB_LIMITED) {
-		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
-						RGB_QUANTIZATION_LIMITED_RANGE;
-		info_frame.avi_info_packet.info_packet_hdmi.bits.YQ0_YQ1 =
-						YYC_QUANTIZATION_LIMITED_RANGE;
+		hdmi_info->bits.Q0_Q1   = RGB_QUANTIZATION_LIMITED_RANGE;
+		hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
 	} else {
-		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
-						RGB_QUANTIZATION_DEFAULT_RANGE;
-		info_frame.avi_info_packet.info_packet_hdmi.bits.YQ0_YQ1 =
-						YYC_QUANTIZATION_LIMITED_RANGE;
+		hdmi_info->bits.Q0_Q1   = RGB_QUANTIZATION_DEFAULT_RANGE;
+		hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
 	}
 
-	info_frame.avi_info_packet.info_packet_hdmi.bits.VIC0_VIC7 =
+	hdmi_info->bits.VIC0_VIC7 =
 					stream->public.timing.vic;
 
 	/* pixel repetition
 	 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
 	 * repetition start from 1 */
-	info_frame.avi_info_packet.info_packet_hdmi.bits.PR0_PR3 = 0;
+	hdmi_info->bits.PR0_PR3 = 0;
 
 	/* Bar Info
 	 * barTop:    Line Number of End of Top Bar.
 	 * barBottom: Line Number of Start of Bottom Bar.
 	 * barLeft:   Pixel Number of End of Left Bar.
 	 * barRight:  Pixel Number of Start of Right Bar. */
-	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_top =
-			stream->public.timing.v_border_top;
-	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_bottom =
-		(stream->public.timing.v_border_top
+	hdmi_info->bits.bar_top = stream->public.timing.v_border_top;
+	hdmi_info->bits.bar_bottom = (stream->public.timing.v_border_top
 			- stream->public.timing.v_border_bottom + 1);
-	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_left =
-			stream->public.timing.h_border_left;
-	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_right =
-		(stream->public.timing.h_total
+	hdmi_info->bits.bar_left  = stream->public.timing.h_border_left;
+	hdmi_info->bits.bar_right = (stream->public.timing.h_total
 			- stream->public.timing.h_border_right + 1);
 
 	/* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
-	check_sum =
-		&info_frame.
-		avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
+	check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
+
 	*check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
 
 	for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
-		*check_sum += info_frame.avi_info_packet.info_packet_hdmi.
-				packet_raw_data.sb[byte_index];
+		*check_sum += hdmi_info->packet_raw_data.sb[byte_index];
 
 	/* one byte complement */
 	*check_sum = (uint8_t) (0x100 - *check_sum);
 
 	/* Store in hw_path_mode */
-	info_packet->hb0 =
-		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb0;
-	info_packet->hb1 =
-		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb1;
-	info_packet->hb2 =
-		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb2;
+	info_packet->hb0 = hdmi_info->packet_raw_data.hb0;
+	info_packet->hb1 = hdmi_info->packet_raw_data.hb1;
+	info_packet->hb2 = hdmi_info->packet_raw_data.hb2;
 
 	for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet.
 				info_packet_hdmi.packet_raw_data.sb); byte_index++)
-- 
2.11.0

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[PATCH v2 06/16] drm/amd/display: Temporary disable PSR for HBR2 & HBR3

[Harry Wentland]

From: Zeyu Fan <Zeyu.Fan@amd.com>

Change-Id: I86c9b7413173324934710b17731f6d2c9f55cbc6
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index d04cad27cfa6..6cfd88086044 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2165,7 +2165,8 @@ static void retrieve_link_cap(struct core_link *link)
 	CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
 
 	/* TODO: Confirm if need retrieve_psr_link_cap */
-	retrieve_psr_link_cap(link, link->edp_revision);
+	if (link->public.reported_link_cap.link_rate < LINK_RATE_HIGH2)
+		retrieve_psr_link_cap(link, link->edp_revision);
 }
 
 void detect_dp_sink_caps(struct core_link *link)
-- 
2.11.0

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[PATCH v2 07/16] drm/amd/display: fix dce_calc surface pitch setting for non underlay pipes

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: Ie5801af2ecdcd9117c7b0a9bb26858d1b5dd3379
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 5ac614f433f8..627b7582394a 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -2614,7 +2614,7 @@ static void populate_initial_data(
 		data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_total);
 		data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->public.timing.pix_clk_khz, 1000);
 		data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width);
-		data->pitch_in_pixels[num_displays + 4] = bw_int_to_fixed(pipe[i].surface->public.plane_size.grph.surface_pitch);
+		data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
 		data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.height);
 		data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.h_taps);
 		data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.v_taps);
@@ -2712,7 +2712,7 @@ static void populate_initial_data(
 		data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->public.timing.pix_clk_khz, 1000);
 		if (pipe[i].surface) {
 			data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width);
-			data->pitch_in_pixels[num_displays + 4] = bw_int_to_fixed(pipe[i].surface->public.plane_size.grph.surface_pitch);
+			data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
 			data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.height);
 			data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.h_taps);
 			data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.v_taps);
-- 
2.11.0

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[PATCH v2 08/16] drm/amd/display: Remove get_connector_for_link.

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

We can keep a 1:1 relation between a link and a physical
connector and hence skip the iteration. This function
is used in context of only physical connetors.

Change-Id: I3379e620b8400f02dc80a50927b66e9e06406579
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c  | 36 +++-------------------
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    |  1 +
 drivers/gpu/drm/amd/display/dc/dc.h                |  2 ++
 3 files changed, 8 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index e503677110c3..961d8d13d725 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -148,21 +148,6 @@ static struct amdgpu_connector *get_connector_for_sink(
 	return NULL;
 }
 
-static struct amdgpu_connector *get_connector_for_link(
-	struct drm_device *dev,
-	const struct dc_link *link)
-{
-	struct drm_connector *connector;
-
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-		struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
-		if (aconnector->dc_link == link)
-			return aconnector;
-	}
-
-	return NULL;
-}
-
 static void get_payload_table(
 		struct amdgpu_connector *aconnector,
 		struct dp_mst_stream_allocation_table *proposed_table)
@@ -362,9 +347,7 @@ bool dm_helpers_dp_mst_start_top_mgr(
 		const struct dc_link *link,
 		bool boot)
 {
-	struct amdgpu_device *adev = ctx->driver_context;
-	struct drm_device *dev = adev->ddev;
-	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
+	struct amdgpu_connector *aconnector = link->priv;
 
 	if (!aconnector) {
 			DRM_ERROR("Failed to found connector for link!");
@@ -387,9 +370,7 @@ void dm_helpers_dp_mst_stop_top_mgr(
 		struct dc_context *ctx,
 		const struct dc_link *link)
 {
-	struct amdgpu_device *adev = ctx->driver_context;
-	struct drm_device *dev = adev->ddev;
-	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
+	struct amdgpu_connector *aconnector = link->priv;
 
 	if (!aconnector) {
 			DRM_ERROR("Failed to found connector for link!");
@@ -411,9 +392,7 @@ bool dm_helpers_dp_read_dpcd(
 		uint32_t size)
 {
 
-	struct amdgpu_device *adev = ctx->driver_context;
-	struct drm_device *dev = adev->ddev;
-	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
+	struct amdgpu_connector *aconnector = link->priv;
 
 	if (!aconnector) {
 		DRM_ERROR("Failed to found connector for link!");
@@ -431,10 +410,7 @@ bool dm_helpers_dp_write_dpcd(
 		const uint8_t *data,
 		uint32_t size)
 {
-
-	struct amdgpu_device *adev = ctx->driver_context;
-	struct drm_device *dev = adev->ddev;
-	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
+	struct amdgpu_connector *aconnector = link->priv;
 
 	if (!aconnector) {
 		DRM_ERROR("Failed to found connector for link!");
@@ -450,9 +426,7 @@ bool dm_helpers_submit_i2c(
 		const struct dc_link *link,
 		struct i2c_command *cmd)
 {
-	struct amdgpu_device *adev = ctx->driver_context;
-	struct drm_device *dev = adev->ddev;
-	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
+	struct amdgpu_connector *aconnector = link->priv;
 	struct i2c_msg *msgs;
 	int i = 0;
 	int num = cmd->number_of_payloads;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 0424b2d65793..5e231c3ff482 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2175,6 +2175,7 @@ int amdgpu_dm_connector_init(
 	struct dc *dc = dm->dc;
 	const struct dc_link *link = dc_get_link_at_index(dc, link_index);
 	struct amdgpu_i2c_adapter *i2c;
+	((struct dc_link *)link)->priv = aconnector;
 
 	DRM_DEBUG_KMS("%s()\n", __func__);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 9dd8b2ad4c59..6bb6ad23b31b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -592,6 +592,8 @@ struct dc_link {
 	struct psr_caps psr_caps;
 	bool test_pattern_enabled;
 	union compliance_test_state compliance_test_state;
+
+	void *priv;
 };
 
 struct dpcd_caps {
-- 
2.11.0

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[PATCH v2 09/16] drm/amd/display: Remove get_connector_for_sink.

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

Keep 1:1 relation between MST sink and it's MST connector.

Change-Id: Iff663ecfe738886b2f96400a1798e7533eb64378
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c  | 27 +++-------------------
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c    |  7 +++++-
 drivers/gpu/drm/amd/display/dc/dc.h                |  1 +
 3 files changed, 10 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 961d8d13d725..5d45c0fe3643 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -133,21 +133,6 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
 	return result;
 }
 
-static struct amdgpu_connector *get_connector_for_sink(
-	struct drm_device *dev,
-	const struct dc_sink *sink)
-{
-	struct drm_connector *connector;
-
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-		struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
-		if (aconnector->dc_sink == sink)
-			return aconnector;
-	}
-
-	return NULL;
-}
-
 static void get_payload_table(
 		struct amdgpu_connector *aconnector,
 		struct dp_mst_stream_allocation_table *proposed_table)
@@ -194,8 +179,6 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
 		struct dp_mst_stream_allocation_table *proposed_table,
 		bool enable)
 {
-	struct amdgpu_device *adev = ctx->driver_context;
-	struct drm_device *dev = adev->ddev;
 	struct amdgpu_connector *aconnector;
 	struct drm_dp_mst_topology_mgr *mst_mgr;
 	struct drm_dp_mst_port *mst_port;
@@ -205,7 +188,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
 	int bpp = 0;
 	int pbn = 0;
 
-	aconnector = get_connector_for_sink(dev, stream->sink);
+	aconnector = stream->sink->priv;
 
 	if (!aconnector || !aconnector->mst_port)
 		return false;
@@ -283,13 +266,11 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
 		struct dc_context *ctx,
 		const struct dc_stream *stream)
 {
-	struct amdgpu_device *adev = ctx->driver_context;
-	struct drm_device *dev = adev->ddev;
 	struct amdgpu_connector *aconnector;
 	struct drm_dp_mst_topology_mgr *mst_mgr;
 	int ret;
 
-	aconnector = get_connector_for_sink(dev, stream->sink);
+	aconnector = stream->sink->priv;
 
 	if (!aconnector || !aconnector->mst_port)
 		return false;
@@ -312,14 +293,12 @@ bool dm_helpers_dp_mst_send_payload_allocation(
 		const struct dc_stream *stream,
 		bool enable)
 {
-	struct amdgpu_device *adev = ctx->driver_context;
-	struct drm_device *dev = adev->ddev;
 	struct amdgpu_connector *aconnector;
 	struct drm_dp_mst_topology_mgr *mst_mgr;
 	struct drm_dp_mst_port *mst_port;
 	int ret;
 
-	aconnector = get_connector_for_sink(dev, stream->sink);
+	aconnector = stream->sink->priv;
 
 	if (!aconnector || !aconnector->mst_port)
 		return false;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 937558d1d7f4..91b3610a3654 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -327,6 +327,7 @@ static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
 	struct drm_connector *connector;
 	struct amdgpu_connector *aconnector;
 	struct edid *edid;
+	struct dc_sink *dc_sink;
 
 	drm_modeset_lock_all(dev);
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
@@ -354,11 +355,15 @@ static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
 
 				aconnector->edid = edid;
 
-				aconnector->dc_sink = dc_link_add_remote_sink(
+				dc_sink = dc_link_add_remote_sink(
 					aconnector->dc_link,
 					(uint8_t *)edid,
 					(edid->extensions + 1) * EDID_LENGTH,
 					&init_params);
+
+				dc_sink->priv = aconnector;
+				aconnector->dc_sink = dc_sink;
+
 				if (aconnector->dc_sink)
 					amdgpu_dm_add_sink_to_freesync_module(
 							connector,
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 6bb6ad23b31b..d2960552c78e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -719,6 +719,7 @@ struct dc_sink {
 	struct dc_container_id *dc_container_id;
 	uint32_t dongle_max_pix_clk;
 	bool converter_disable_audio;
+	void *priv;
 };
 
 void dc_sink_retain(const struct dc_sink *sink);
-- 
2.11.0

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[PATCH v2 10/16] drm/amd/display: Fix i2c write flag.

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

I2C_M_RD was translated to write instead of read.

Change-Id: I49e819ca6d8519d91eb13b371d773b2eb1b601e5
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 5d45c0fe3643..ca4fa5c8d8bf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -422,7 +422,7 @@ bool dm_helpers_submit_i2c(
 		return false;
 
 	for (i = 0; i < num; i++) {
-		msgs[i].flags = cmd->payloads[i].write ? I2C_M_RD : 0;
+		msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
 		msgs[i].addr = cmd->payloads[i].address;
 		msgs[i].len = cmd->payloads[i].length;
 		msgs[i].buf = cmd->payloads[i].data;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 5e231c3ff482..a260bb5fad3b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2121,7 +2121,7 @@ int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
 	cmd.speed = 100;
 
 	for (i = 0; i < num; i++) {
-		cmd.payloads[i].write = (msgs[i].flags & I2C_M_RD);
+		cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
 		cmd.payloads[i].address = msgs[i].addr;
 		cmd.payloads[i].length = msgs[i].len;
 		cmd.payloads[i].data = msgs[i].buf;
-- 
2.11.0

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[PATCH v2 11/16] drm/amd/display: Refactor edid read.

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

Allow Linux to use DRM provided EDID read functioality
by moving  DAL edid implementation to module hence
removing this code from DC by this cleaning up DC
code for upstream.

v2: Removing ddc_service. No more need for it.

Change-Id: I7c73ae63102fa06f86b347f21ee28902ca4f7c58
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c  |  47 +++
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c    |  47 ++-
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.h    |   2 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    |  10 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c           |  78 +++--
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      |  53 +---
 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c  | 337 +--------------------
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   |  30 +-
 drivers/gpu/drm/amd/display/dc/dc.h                |  21 +-
 drivers/gpu/drm/amd/display/dc/dc_types.h          |   6 +
 drivers/gpu/drm/amd/display/dc/dm_helpers.h        |  10 +
 drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c     |   9 +-
 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h   |  38 ++-
 .../drm/amd/display/include/ddc_service_types.h    |  28 --
 .../gpu/drm/amd/display/include/i2caux_interface.h |   3 +
 15 files changed, 254 insertions(+), 465 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index ca4fa5c8d8bf..3401780af2d3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -434,3 +434,50 @@ bool dm_helpers_submit_i2c(
 
 	return result;
 }
+
+enum dc_edid_status dm_helpers_read_local_edid(
+		struct dc_context *ctx,
+		struct dc_link *link,
+		struct dc_sink *sink)
+{
+	struct amdgpu_connector *aconnector = link->priv;
+	struct i2c_adapter *ddc;
+	int retry = 3;
+	enum dc_edid_status edid_status;
+	struct edid *edid;
+
+	if (link->aux_mode)
+		ddc = &aconnector->dm_dp_aux.aux.ddc;
+	else
+		ddc = &aconnector->i2c->base;
+
+	/* some dongles read edid incorrectly the first time,
+	 * do check sum and retry to make sure read correct edid.
+	 */
+	do {
+
+		edid = drm_get_edid(&aconnector->base, ddc);
+
+		if (!edid)
+			return EDID_NO_RESPONSE;
+
+		sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
+		memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
+
+		/* We don't need the original edid anymore */
+		kfree(edid);
+
+		edid_status = dm_helpers_parse_edid_caps(
+						ctx,
+						&sink->dc_edid,
+						&sink->edid_caps);
+
+	} while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
+
+	if (edid_status != EDID_OK)
+		DRM_ERROR("EDID err: %d, on connector: %s",
+				edid_status,
+				aconnector->base.name);
+
+	return edid_status;
+}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 91b3610a3654..0e79ba920b06 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -81,24 +81,43 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg
 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 	struct amdgpu_device *adev = drm_dev->dev_private;
 	struct dc *dc = adev->dm.dc;
+	enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ? I2C_MOT_TRUE : I2C_MOT_FALSE;
 	bool res;
 
-	switch (msg->request) {
+	switch (msg->request & ~DP_AUX_I2C_MOT) {
 	case DP_AUX_NATIVE_READ:
-		res = dc_read_dpcd(
-			dc,
-			TO_DM_AUX(aux)->link_index,
-			msg->address,
-			msg->buffer,
-			msg->size);
+		res = dc_read_aux_dpcd(
+				dc,
+				TO_DM_AUX(aux)->link_index,
+				msg->address,
+				msg->buffer,
+				msg->size);
 		break;
 	case DP_AUX_NATIVE_WRITE:
-		res = dc_write_dpcd(
-			dc,
-			TO_DM_AUX(aux)->link_index,
-			msg->address,
-			msg->buffer,
-			msg->size);
+		res = dc_write_aux_dpcd(
+				dc,
+				TO_DM_AUX(aux)->link_index,
+				msg->address,
+				msg->buffer,
+				msg->size);
+		break;
+	case DP_AUX_I2C_READ:
+		res = dc_read_aux_i2c(
+				dc,
+				TO_DM_AUX(aux)->link_index,
+				mot,
+				msg->address,
+				msg->buffer,
+				msg->size);
+		break;
+	case DP_AUX_I2C_WRITE:
+		res = dc_write_aux_i2c(
+				dc,
+				TO_DM_AUX(aux)->link_index,
+				mot,
+				msg->address,
+				msg->buffer,
+				msg->size);
 		break;
 	default:
 		return 0;
@@ -420,7 +439,7 @@ static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 	.register_connector = dm_dp_mst_register_connector
 };
 
-void amdgpu_dm_initialize_mst_connector(
+void amdgpu_dm_initialize_dp_connector(
 	struct amdgpu_display_manager *dm,
 	struct amdgpu_connector *aconnector)
 {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index 6130d62ac65c..418061f3b46b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -29,7 +29,7 @@
 struct amdgpu_display_manager;
 struct amdgpu_connector;
 
-void amdgpu_dm_initialize_mst_connector(
+void amdgpu_dm_initialize_dp_connector(
 	struct amdgpu_display_manager *dm,
 	struct amdgpu_connector *aconnector);
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index a260bb5fad3b..4904d1157621 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2220,7 +2220,7 @@ int amdgpu_dm_connector_init(
 
 	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
 		|| connector_type == DRM_MODE_CONNECTOR_eDP)
-		amdgpu_dm_initialize_mst_connector(dm, aconnector);
+		amdgpu_dm_initialize_dp_connector(dm, aconnector);
 
 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
 	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
@@ -3211,9 +3211,11 @@ static bool is_dp_capable_without_timing_msa(
 	uint8_t dpcd_data;
 	bool capable = false;
 	if (amdgpu_connector->dc_link &&
-	    dc_read_dpcd(dc, amdgpu_connector->dc_link->link_index,
-			 DP_DOWN_STREAM_PORT_COUNT,
-			 &dpcd_data, sizeof(dpcd_data)) )
+		dc_read_aux_dpcd(
+			dc,
+			amdgpu_connector->dc_link->link_index,
+			DP_DOWN_STREAM_PORT_COUNT,
+			&dpcd_data, sizeof(dpcd_data)))
 		capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
 
 	return capable;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index b3891228b499..40a800155fe6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1553,7 +1553,7 @@ void dc_resume(const struct dc *dc)
 		core_link_resume(core_dc->links[i]);
 }
 
-bool dc_read_dpcd(
+bool dc_read_aux_dpcd(
 		struct dc *dc,
 		uint32_t link_index,
 		uint32_t address,
@@ -1565,56 +1565,100 @@ bool dc_read_dpcd(
 	struct core_link *link = core_dc->links[link_index];
 	enum ddc_result r = dal_ddc_service_read_dpcd_data(
 			link->ddc,
+			false,
+			I2C_MOT_UNDEF,
 			address,
 			data,
 			size);
 	return r == DDC_RESULT_SUCESSFULL;
 }
 
-bool dc_query_ddc_data(
+bool dc_write_aux_dpcd(
 		struct dc *dc,
 		uint32_t link_index,
 		uint32_t address,
-		uint8_t *write_buf,
-		uint32_t write_size,
-		uint8_t *read_buf,
-		uint32_t read_size) {
-
+		const uint8_t *data,
+		uint32_t size)
+{
 	struct core_dc *core_dc = DC_TO_CORE(dc);
-
 	struct core_link *link = core_dc->links[link_index];
 
-	bool result = dal_ddc_service_query_ddc_data(
+	enum ddc_result r = dal_ddc_service_write_dpcd_data(
 			link->ddc,
+			false,
+			I2C_MOT_UNDEF,
 			address,
-			write_buf,
-			write_size,
-			read_buf,
-			read_size);
-
-	return result;
+			data,
+			size);
+	return r == DDC_RESULT_SUCESSFULL;
 }
 
+bool dc_read_aux_i2c(
+		struct dc *dc,
+		uint32_t link_index,
+		enum i2c_mot_mode mot,
+		uint32_t address,
+		uint8_t *data,
+		uint32_t size)
+{
+	struct core_dc *core_dc = DC_TO_CORE(dc);
 
-bool dc_write_dpcd(
+		struct core_link *link = core_dc->links[link_index];
+		enum ddc_result r = dal_ddc_service_read_dpcd_data(
+			link->ddc,
+			true,
+			mot,
+			address,
+			data,
+			size);
+		return r == DDC_RESULT_SUCESSFULL;
+}
+
+bool dc_write_aux_i2c(
 		struct dc *dc,
 		uint32_t link_index,
+		enum i2c_mot_mode mot,
 		uint32_t address,
 		const uint8_t *data,
 		uint32_t size)
 {
 	struct core_dc *core_dc = DC_TO_CORE(dc);
-
 	struct core_link *link = core_dc->links[link_index];
 
 	enum ddc_result r = dal_ddc_service_write_dpcd_data(
 			link->ddc,
+			true,
+			mot,
 			address,
 			data,
 			size);
 	return r == DDC_RESULT_SUCESSFULL;
 }
 
+bool dc_query_ddc_data(
+		struct dc *dc,
+		uint32_t link_index,
+		uint32_t address,
+		uint8_t *write_buf,
+		uint32_t write_size,
+		uint8_t *read_buf,
+		uint32_t read_size) {
+
+	struct core_dc *core_dc = DC_TO_CORE(dc);
+
+	struct core_link *link = core_dc->links[link_index];
+
+	bool result = dal_ddc_service_query_ddc_data(
+			link->ddc,
+			address,
+			write_buf,
+			write_size,
+			read_buf,
+			read_size);
+
+	return result;
+}
+
 bool dc_submit_i2c(
 		struct dc *dc,
 		uint32_t link_index,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 74dd272d7452..0f825f6326ab 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -464,39 +464,6 @@ static void link_disconnect_sink(struct core_link *link)
 	link->dpcd_sink_count = 0;
 }
 
-static enum dc_edid_status read_edid(
-	struct core_link *link,
-	struct core_sink *sink)
-{
-	uint32_t edid_retry = 3;
-	enum dc_edid_status edid_status;
-
-	/* some dongles read edid incorrectly the first time,
-	 * do check sum and retry to make sure read correct edid.
-	 */
-	do {
-		sink->public.dc_edid.length =
-				dal_ddc_service_edid_query(link->ddc);
-
-		if (0 == sink->public.dc_edid.length)
-			return EDID_NO_RESPONSE;
-
-		dal_ddc_service_get_edid_buf(link->ddc,
-				sink->public.dc_edid.raw_edid);
-		edid_status = dm_helpers_parse_edid_caps(
-				sink->ctx,
-				&sink->public.dc_edid,
-				&sink->public.edid_caps);
-		--edid_retry;
-		if (edid_status == EDID_BAD_CHECKSUM)
-			dm_logger_write(link->ctx->logger, LOG_WARNING,
-					"Bad EDID checksum, retry remain: %d\n",
-					edid_retry);
-	} while (edid_status == EDID_BAD_CHECKSUM && edid_retry > 0);
-
-	return edid_status;
-}
-
 static void detect_dp(
 	struct core_link *link,
 	struct display_sink_capability *sink_caps,
@@ -673,6 +640,9 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
 						link->ddc,
 						sink_caps.transaction_type);
 
+		link->public.aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
+				link->ddc);
+
 		sink_init_data.link = &link->public;
 		sink_init_data.sink_signal = sink_caps.signal;
 
@@ -688,7 +658,10 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
 		sink = DC_SINK_TO_CORE(dc_sink);
 		link->public.local_sink = &sink->public;
 
-		edid_status = read_edid(link, sink);
+		edid_status = dm_helpers_read_local_edid(
+				link->ctx,
+				&link->public,
+				&sink->public);
 
 		switch (edid_status) {
 		case EDID_BAD_CHECKSUM:
@@ -1500,11 +1473,13 @@ bool dc_link_setup_psr(const struct dc_link *dc_link,
 			 */
 			psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
 		}
-		dal_ddc_service_write_dpcd_data(
-					link->ddc,
-					368,
-					&psr_configuration.raw,
-					sizeof(psr_configuration.raw));
+
+		dm_helpers_dp_write_dpcd(
+			link->ctx,
+			dc_link,
+			368,
+			&psr_configuration.raw,
+			sizeof(psr_configuration.raw));
 
 		psr_context.channel = link->ddc->ddc_pin->hw_info.ddc_channel;
 		if (psr_context.channel == 0)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 4e9465b630d1..2f5a89c5b063 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -58,30 +58,6 @@ struct dp_hdmi_dongle_signature_data {
 	uint8_t eot;/* end of transmition '\x4' */
 };
 
-/* Address range from 0x00 to 0x1F.*/
-#define DP_ADAPTOR_TYPE2_SIZE 0x20
-#define DP_ADAPTOR_TYPE2_REG_ID 0x10
-#define DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK 0x1D
-/* Identifies adaptor as Dual-mode adaptor */
-#define DP_ADAPTOR_TYPE2_ID 0xA0
-/* MHz*/
-#define DP_ADAPTOR_TYPE2_MAX_TMDS_CLK 600
-/* MHz*/
-#define DP_ADAPTOR_TYPE2_MIN_TMDS_CLK 25
-/* kHZ*/
-#define DP_ADAPTOR_DVI_MAX_TMDS_CLK 165000
-/* kHZ*/
-#define DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK 165000
-
-#define DDC_I2C_COMMAND_ENGINE I2C_COMMAND_ENGINE_SW
-
-enum edid_read_result {
-	EDID_READ_RESULT_EDID_MATCH = 0,
-	EDID_READ_RESULT_EDID_MISMATCH,
-	EDID_READ_RESULT_CHECKSUM_READ_ERR,
-	EDID_READ_RESULT_VENDOR_READ_ERR
-};
-
 /* SCDC Address defines (HDMI 2.0)*/
 #define HDMI_SCDC_WRITE_UPDATE_0_ARRAY 3
 #define HDMI_SCDC_ADDRESS  0x54
@@ -392,7 +368,7 @@ static uint32_t defer_delay_converter_wa(
 
 #define DP_TRANSLATOR_DELAY 5
 
-static uint32_t get_defer_delay(struct ddc_service *ddc)
+uint32_t get_defer_delay(struct ddc_service *ddc)
 {
 	uint32_t defer_delay = 0;
 
@@ -451,307 +427,6 @@ static bool i2c_read(
 			&command);
 }
 
-static uint8_t aux_read_edid_block(
-	struct ddc_service *ddc,
-	uint8_t address,
-	uint8_t index,
-	uint8_t *buf)
-{
-	struct aux_command cmd = {
-		.payloads = NULL,
-		.number_of_payloads = 0,
-		.defer_delay = get_defer_delay(ddc),
-		.max_defer_write_retry = 0 };
-
-	uint8_t retrieved = 0;
-	uint8_t base_offset =
-		(index % DDC_EDID_BLOCKS_PER_SEGMENT) * DDC_EDID_BLOCK_SIZE;
-	uint8_t segment = index / DDC_EDID_BLOCKS_PER_SEGMENT;
-
-	for (retrieved = 0; retrieved < DDC_EDID_BLOCK_SIZE;
-		retrieved += DEFAULT_AUX_MAX_DATA_SIZE) {
-
-		uint8_t offset = base_offset + retrieved;
-
-		struct aux_payload payloads[3] = {
-			{
-			.i2c_over_aux = true,
-			.write = true,
-			.address = DDC_EDID_SEGMENT_ADDRESS,
-			.length = 1,
-			.data = &segment },
-			{
-			.i2c_over_aux = true,
-			.write = true,
-			.address = address,
-			.length = 1,
-			.data = &offset },
-			{
-			.i2c_over_aux = true,
-			.write = false,
-			.address = address,
-			.length = DEFAULT_AUX_MAX_DATA_SIZE,
-			.data = &buf[retrieved] } };
-
-		if (segment == 0) {
-			cmd.payloads = &payloads[1];
-			cmd.number_of_payloads = 2;
-		} else {
-			cmd.payloads = payloads;
-			cmd.number_of_payloads = 3;
-		}
-
-		if (!dal_i2caux_submit_aux_command(
-			ddc->ctx->i2caux,
-			ddc->ddc_pin,
-			&cmd))
-			/* cannot read, break*/
-			break;
-	}
-
-	/* Reset segment to 0. Needed by some panels */
-	if (0 != segment) {
-		struct aux_payload payloads[1] = { {
-			.i2c_over_aux = true,
-			.write = true,
-			.address = DDC_EDID_SEGMENT_ADDRESS,
-			.length = 1,
-			.data = &segment } };
-		bool result = false;
-
-		segment = 0;
-
-		cmd.number_of_payloads = ARRAY_SIZE(payloads);
-		cmd.payloads = payloads;
-
-		result = dal_i2caux_submit_aux_command(
-			ddc->ctx->i2caux,
-			ddc->ddc_pin,
-			&cmd);
-
-		if (false == result)
-			dm_logger_write(
-				ddc->ctx->logger, LOG_ERROR,
-				"%s: Writing of EDID Segment (0x30) failed!\n",
-				__func__);
-	}
-
-	return retrieved;
-}
-
-static uint8_t i2c_read_edid_block(
-	struct ddc_service *ddc,
-	uint8_t address,
-	uint8_t index,
-	uint8_t *buf)
-{
-	bool ret = false;
-	uint8_t offset = (index % DDC_EDID_BLOCKS_PER_SEGMENT) *
-		DDC_EDID_BLOCK_SIZE;
-	uint8_t segment = index / DDC_EDID_BLOCKS_PER_SEGMENT;
-
-	struct i2c_command cmd = {
-		.payloads = NULL,
-		.number_of_payloads = 0,
-		.engine = DDC_I2C_COMMAND_ENGINE,
-		.speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
-
-	struct i2c_payload payloads[3] = {
-		{
-		.write = true,
-		.address = DDC_EDID_SEGMENT_ADDRESS,
-		.length = 1,
-		.data = &segment },
-		{
-		.write = true,
-		.address = address,
-		.length = 1,
-		.data = &offset },
-		{
-		.write = false,
-		.address = address,
-		.length = DDC_EDID_BLOCK_SIZE,
-		.data = buf } };
-/*
- * Some I2C engines don't handle stop/start between write-offset and read-data
- * commands properly. For those displays, we have to force the newer E-DDC
- * behavior of repeated-start which can be enabled by runtime parameter. */
-/* Originally implemented for OnLive using NXP receiver chip */
-
-	if (index == 0 && !ddc->flags.FORCE_READ_REPEATED_START) {
-		/* base block, use use DDC2B, submit as 2 commands */
-		cmd.payloads = &payloads[1];
-		cmd.number_of_payloads = 1;
-
-		if (dm_helpers_submit_i2c(
-			ddc->ctx,
-			&ddc->link->public,
-			&cmd)) {
-
-			cmd.payloads = &payloads[2];
-			cmd.number_of_payloads = 1;
-
-			ret = dm_helpers_submit_i2c(
-					ddc->ctx,
-					&ddc->link->public,
-					&cmd);
-		}
-
-	} else {
-		/*
-		 * extension block use E-DDC, submit as 1 command
-		 * or if repeated-start is forced by runtime parameter
-		 */
-		if (segment != 0) {
-			/* include segment offset in command*/
-			cmd.payloads = payloads;
-			cmd.number_of_payloads = 3;
-		} else {
-			/* we are reading first segment,
-			 * segment offset is not required */
-			cmd.payloads = &payloads[1];
-			cmd.number_of_payloads = 2;
-		}
-
-		ret = dm_helpers_submit_i2c(
-				ddc->ctx,
-				&ddc->link->public,
-				&cmd);
-	}
-
-	return ret ? DDC_EDID_BLOCK_SIZE : 0;
-}
-
-static uint32_t query_edid_block(
-	struct ddc_service *ddc,
-	uint8_t address,
-	uint8_t index,
-	uint8_t *buf,
-	uint32_t size)
-{
-	uint32_t size_retrieved = 0;
-
-	if (size < DDC_EDID_BLOCK_SIZE)
-		return 0;
-
-	if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
-		size_retrieved =
-			aux_read_edid_block(ddc, address, index, buf);
-	} else {
-		size_retrieved =
-			i2c_read_edid_block(ddc, address, index, buf);
-	}
-
-	return size_retrieved;
-}
-
-#define DDC_DPCD_EDID_CHECKSUM_WRITE_ADDRESS 0x261
-#define DDC_TEST_ACK_ADDRESS 0x260
-#define DDC_DPCD_EDID_TEST_ACK 0x04
-#define DDC_DPCD_EDID_TEST_MASK 0x04
-#define DDC_DPCD_TEST_REQUEST_ADDRESS 0x218
-
-/* AG TODO GO throug DM callback here like for DPCD */
-
-static void write_dp_edid_checksum(
-	struct ddc_service *ddc,
-	uint8_t checksum)
-{
-	uint8_t dpcd_data;
-
-	dal_ddc_service_read_dpcd_data(
-		ddc,
-		DDC_DPCD_TEST_REQUEST_ADDRESS,
-		&dpcd_data,
-		1);
-
-	if (dpcd_data & DDC_DPCD_EDID_TEST_MASK) {
-
-		dal_ddc_service_write_dpcd_data(
-			ddc,
-			DDC_DPCD_EDID_CHECKSUM_WRITE_ADDRESS,
-			&checksum,
-			1);
-
-		dpcd_data = DDC_DPCD_EDID_TEST_ACK;
-
-		dal_ddc_service_write_dpcd_data(
-			ddc,
-			DDC_TEST_ACK_ADDRESS,
-			&dpcd_data,
-			1);
-	}
-}
-
-uint32_t dal_ddc_service_edid_query(struct ddc_service *ddc)
-{
-	uint32_t bytes_read = 0;
-	uint32_t ext_cnt = 0;
-
-	uint8_t address;
-	uint32_t i;
-
-	for (address = DDC_EDID_ADDRESS_START;
-		address <= DDC_EDID_ADDRESS_END; ++address) {
-
-		bytes_read = query_edid_block(
-			ddc,
-			address,
-			0,
-			ddc->edid_buf,
-			sizeof(ddc->edid_buf) - bytes_read);
-
-		if (bytes_read != DDC_EDID_BLOCK_SIZE)
-			continue;
-
-		/* get the number of ext blocks*/
-		ext_cnt = ddc->edid_buf[DDC_EDID_EXT_COUNT_OFFSET];
-
-		/* EDID 2.0, need to read 1 more block because EDID2.0 is
-		 * 256 byte in size*/
-		if (ddc->edid_buf[DDC_EDID_20_SIGNATURE_OFFSET] ==
-			DDC_EDID_20_SIGNATURE)
-				ext_cnt = 1;
-
-		for (i = 0; i < ext_cnt; i++) {
-			/* read additional ext blocks accordingly */
-			bytes_read += query_edid_block(
-					ddc,
-					address,
-					i+1,
-					&ddc->edid_buf[bytes_read],
-					sizeof(ddc->edid_buf) - bytes_read);
-		}
-
-		/*this is special code path for DP compliance*/
-		if (DDC_TRANSACTION_TYPE_I2C_OVER_AUX == ddc->transaction_type)
-			write_dp_edid_checksum(
-				ddc,
-				ddc->edid_buf[(ext_cnt * DDC_EDID_BLOCK_SIZE) +
-				DDC_EDID1X_CHECKSUM_OFFSET]);
-
-		/*remembers the address where we fetch the EDID from
-		 * for later signature check use */
-		ddc->address = address;
-
-		break;/* already read edid, done*/
-	}
-
-	ddc->edid_buf_len = bytes_read;
-	return bytes_read;
-}
-
-uint32_t dal_ddc_service_get_edid_buf_len(struct ddc_service *ddc)
-{
-	return ddc->edid_buf_len;
-}
-
-void dal_ddc_service_get_edid_buf(struct ddc_service *ddc, uint8_t *edid_buf)
-{
-	memmove(edid_buf,
-			ddc->edid_buf, ddc->edid_buf_len);
-}
-
 void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 	struct ddc_service *ddc,
 	struct display_sink_capability *sink_cap)
@@ -960,12 +635,14 @@ bool dal_ddc_service_query_ddc_data(
 
 enum ddc_result dal_ddc_service_read_dpcd_data(
 	struct ddc_service *ddc,
+	bool i2c,
+	enum i2c_mot_mode mot,
 	uint32_t address,
 	uint8_t *data,
 	uint32_t len)
 {
 	struct aux_payload read_payload = {
-		.i2c_over_aux = false,
+		.i2c_over_aux = i2c,
 		.write = false,
 		.address = address,
 		.length = len,
@@ -976,6 +653,7 @@ enum ddc_result dal_ddc_service_read_dpcd_data(
 		.number_of_payloads = 1,
 		.defer_delay = 0,
 		.max_defer_write_retry = 0,
+		.mot = mot
 	};
 
 	if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
@@ -994,12 +672,14 @@ enum ddc_result dal_ddc_service_read_dpcd_data(
 
 enum ddc_result dal_ddc_service_write_dpcd_data(
 	struct ddc_service *ddc,
+	bool i2c,
+	enum i2c_mot_mode mot,
 	uint32_t address,
 	const uint8_t *data,
 	uint32_t len)
 {
 	struct aux_payload write_payload = {
-		.i2c_over_aux = false,
+		.i2c_over_aux = i2c,
 		.write = true,
 		.address = address,
 		.length = len,
@@ -1010,6 +690,7 @@ enum ddc_result dal_ddc_service_write_dpcd_data(
 		.number_of_payloads = 1,
 		.defer_delay = 0,
 		.max_defer_write_retry = 0,
+		.mot = mot
 	};
 
 	if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 6cfd88086044..802d8cc99ea3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1481,22 +1481,25 @@ static bool handle_hpd_irq_psr_sink(const struct core_link *link)
 	if (link->public.psr_caps.psr_version == 0)
 		return false;
 
-	dal_ddc_service_read_dpcd_data(
-					link->ddc,
-					368 /*DpcdAddress_PSR_Enable_Cfg*/,
-					&psr_configuration.raw,
-					sizeof(psr_configuration.raw));
+	dm_helpers_dp_read_dpcd(
+		link->ctx,
+		&link->public,
+		368,/*DpcdAddress_PSR_Enable_Cfg*/
+		&psr_configuration.raw,
+		sizeof(psr_configuration.raw));
+
 
 	if (psr_configuration.bits.ENABLE) {
 		unsigned char dpcdbuf[3] = {0};
 		union psr_error_status psr_error_status;
 		union psr_sink_psr_status psr_sink_psr_status;
 
-		dal_ddc_service_read_dpcd_data(
-					link->ddc,
-					0x2006 /*DpcdAddress_PSR_Error_Status*/,
-					(unsigned char *) dpcdbuf,
-					sizeof(dpcdbuf));
+		dm_helpers_dp_read_dpcd(
+			link->ctx,
+			&link->public,
+			0x2006, /*DpcdAddress_PSR_Error_Status*/
+			(unsigned char *) dpcdbuf,
+			sizeof(dpcdbuf));
 
 		/*DPCD 2006h   ERROR STATUS*/
 		psr_error_status.raw = dpcdbuf[0];
@@ -1506,9 +1509,10 @@ static bool handle_hpd_irq_psr_sink(const struct core_link *link)
 		if (psr_error_status.bits.LINK_CRC_ERROR ||
 				psr_error_status.bits.RFB_STORAGE_ERROR) {
 			/* Acknowledge and clear error bits */
-			dal_ddc_service_write_dpcd_data(
-				link->ddc,
-				8198 /*DpcdAddress_PSR_Error_Status*/,
+			dm_helpers_dp_write_dpcd(
+				link->ctx,
+				&link->public,
+				8198,/*DpcdAddress_PSR_Error_Status*/
 				&psr_error_status.raw,
 				sizeof(psr_error_status.raw));
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index d2960552c78e..a27a6aba0df1 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -594,6 +594,7 @@ struct dc_link {
 	union compliance_test_state compliance_test_state;
 
 	void *priv;
+	bool aux_mode;
 };
 
 struct dpcd_caps {
@@ -788,20 +789,36 @@ const struct ddc_service *dc_get_ddc_at_index(
  * DPCD access interfaces
  */
 
-bool dc_read_dpcd(
+bool dc_read_aux_dpcd(
 		struct dc *dc,
 		uint32_t link_index,
 		uint32_t address,
 		uint8_t *data,
 		uint32_t size);
 
-bool dc_write_dpcd(
+bool dc_write_aux_dpcd(
 		struct dc *dc,
 		uint32_t link_index,
 		uint32_t address,
 		const uint8_t *data,
 		uint32_t size);
 
+bool dc_read_aux_i2c(
+		struct dc *dc,
+		uint32_t link_index,
+		enum i2c_mot_mode mot,
+		uint32_t address,
+		uint8_t *data,
+		uint32_t size);
+
+bool dc_write_aux_i2c(
+		struct dc *dc,
+		uint32_t link_index,
+		enum i2c_mot_mode mot,
+		uint32_t address,
+		const uint8_t *data,
+		uint32_t size);
+
 bool dc_query_ddc_data(
 		struct dc *dc,
 		uint32_t link_index,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 242dd7b3b6b1..e0436e317341 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -489,4 +489,10 @@ struct psr_caps {
 	unsigned int psr_sdp_transmit_line_num_deadline;
 };
 
+enum i2c_mot_mode {
+	I2C_MOT_UNDEF,
+	I2C_MOT_TRUE,
+	I2C_MOT_FALSE
+};
+
 #endif /* DC_TYPES_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
index d6c52d31f0f0..c15a25ce8049 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
@@ -98,4 +98,14 @@ bool dm_helpers_submit_i2c(
 		struct i2c_command *cmd);
 
 
+
+
+
+
+enum dc_edid_status dm_helpers_read_local_edid(
+		struct dc_context *ctx,
+		struct dc_link *link,
+		struct dc_sink *sink);
+
+
 #endif /* __DM_HELPERS__ */
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
index bd84b932aaae..0743265e933c 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
@@ -185,6 +185,7 @@ bool dal_i2caux_submit_aux_command(
 	struct aux_engine *engine;
 	uint8_t index_of_payload = 0;
 	bool result;
+	bool mot;
 
 	if (!ddc) {
 		BREAK_TO_DEBUGGER();
@@ -207,12 +208,14 @@ bool dal_i2caux_submit_aux_command(
 	result = true;
 
 	while (index_of_payload < cmd->number_of_payloads) {
-		bool mot = (index_of_payload != cmd->number_of_payloads - 1);
-
 		struct aux_payload *payload = cmd->payloads + index_of_payload;
-
 		struct i2caux_transaction_request request = { 0 };
 
+		if (cmd->mot == I2C_MOT_UNDEF)
+			mot = (index_of_payload != cmd->number_of_payloads - 1);
+		else
+			mot = (cmd->mot == I2C_MOT_TRUE);
+
 		request.operation = payload->write ?
 			I2CAUX_TRANSACTION_WRITE :
 			I2CAUX_TRANSACTION_READ;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
index 830fc3d039c9..9c2f670c3dc3 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
@@ -31,6 +31,23 @@
 
 #define EDID_SEGMENT_SIZE 256
 
+/* Address range from 0x00 to 0x1F.*/
+#define DP_ADAPTOR_TYPE2_SIZE 0x20
+#define DP_ADAPTOR_TYPE2_REG_ID 0x10
+#define DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK 0x1D
+/* Identifies adaptor as Dual-mode adaptor */
+#define DP_ADAPTOR_TYPE2_ID 0xA0
+/* MHz*/
+#define DP_ADAPTOR_TYPE2_MAX_TMDS_CLK 600
+/* MHz*/
+#define DP_ADAPTOR_TYPE2_MIN_TMDS_CLK 25
+/* kHZ*/
+#define DP_ADAPTOR_DVI_MAX_TMDS_CLK 165000
+/* kHZ*/
+#define DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK 165000
+
+#define DDC_I2C_COMMAND_ENGINE I2C_COMMAND_ENGINE_SW
+
 struct ddc_service;
 struct graphics_object_id;
 enum ddc_result;
@@ -83,12 +100,6 @@ void dal_ddc_service_set_transaction_type(
 
 bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc);
 
-uint32_t dal_ddc_service_edid_query(struct ddc_service *ddc);
-
-uint32_t dal_ddc_service_get_edid_buf_len(struct ddc_service *ddc);
-
-void dal_ddc_service_get_edid_buf(struct ddc_service *ddc, uint8_t *edid_buf);
-
 void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 		struct ddc_service *ddc,
 		struct display_sink_capability *sink_cap);
@@ -103,12 +114,16 @@ bool dal_ddc_service_query_ddc_data(
 
 enum ddc_result dal_ddc_service_read_dpcd_data(
 		struct ddc_service *ddc,
+		bool i2c,
+		enum i2c_mot_mode mot,
 		uint32_t address,
 		uint8_t *data,
 		uint32_t len);
 
 enum ddc_result dal_ddc_service_write_dpcd_data(
 		struct ddc_service *ddc,
+		bool i2c,
+		enum i2c_mot_mode mot,
 		uint32_t address,
 		const uint8_t *data,
 		uint32_t len);
@@ -130,16 +145,7 @@ void dal_ddc_service_set_ddc_pin(
 
 struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service);
 
-enum ddc_result dal_ddc_service_read_dpcd_data(
-		struct ddc_service *ddc,
-		uint32_t address,
-		uint8_t *data,
-		uint32_t len);
-enum ddc_result dal_ddc_service_write_dpcd_data(
-		struct ddc_service *ddc,
-		uint32_t address,
-		const uint8_t *data,
-		uint32_t len);
+uint32_t get_defer_delay(struct ddc_service *ddc);
 
 #endif /* __DAL_DDC_SERVICE_H__ */
 
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index effe03b8f418..0ff2a899b8f7 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -115,34 +115,6 @@ struct av_sync_data {
 	uint8_t aud_del_ins3;/* DPCD 0002Dh */
 };
 
-/** EDID retrieval related constants, also used by MstMgr **/
-
-#define DDC_EDID_SEGMENT_SIZE 256
-#define DDC_EDID_BLOCK_SIZE 128
-#define DDC_EDID_BLOCKS_PER_SEGMENT \
-	(DDC_EDID_SEGMENT_SIZE / DDC_EDID_BLOCK_SIZE)
-
-#define DDC_EDID_EXT_COUNT_OFFSET 0x7E
-
-#define DDC_EDID_ADDRESS_START 0x50
-#define DDC_EDID_ADDRESS_END 0x52
-#define DDC_EDID_SEGMENT_ADDRESS 0x30
-
-/* signatures for Edid 1x */
-#define DDC_EDID1X_VENDORID_SIGNATURE_OFFSET 8
-#define DDC_EDID1X_VENDORID_SIGNATURE_LEN 4
-#define DDC_EDID1X_EXT_CNT_AND_CHECKSUM_OFFSET 126
-#define DDC_EDID1X_EXT_CNT_AND_CHECKSUM_LEN 2
-#define DDC_EDID1X_CHECKSUM_OFFSET 127
-/* signatures for Edid 20*/
-#define DDC_EDID_20_SIGNATURE_OFFSET 0
-#define DDC_EDID_20_SIGNATURE 0x20
-
-#define DDC_EDID20_VENDORID_SIGNATURE_OFFSET 1
-#define DDC_EDID20_VENDORID_SIGNATURE_LEN 4
-#define DDC_EDID20_CHECKSUM_OFFSET 255
-#define DDC_EDID20_CHECKSUM_LEN 1
-
 /*DP to VGA converter*/
 static const uint8_t DP_VGA_CONVERTER_ID_1[] = "mVGAa";
 /*DP to Dual link DVI converter*/
diff --git a/drivers/gpu/drm/amd/display/include/i2caux_interface.h b/drivers/gpu/drm/amd/display/include/i2caux_interface.h
index d2ec04d1c592..13a3c82d118f 100644
--- a/drivers/gpu/drm/amd/display/include/i2caux_interface.h
+++ b/drivers/gpu/drm/amd/display/include/i2caux_interface.h
@@ -26,6 +26,7 @@
 #ifndef __DAL_I2CAUX_INTERFACE_H__
 #define __DAL_I2CAUX_INTERFACE_H__
 
+#include "dc_types.h"
 #include "gpio_service_interface.h"
 
 
@@ -54,6 +55,8 @@ struct aux_command {
 
 	/* zero means "use default value" */
 	uint32_t max_defer_write_retry;
+
+	enum i2c_mot_mode mot;
 };
 
 union aux_config {
-- 
2.11.0

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[PATCH v2 12/16] drm/amd/display: PSR Aux Channel and Static Screen Support Fix

[Harry Wentland]

From: Amy Zhang <Amy.Zhang@amd.com>

- Correct the aux channel selection according to DAL3

Change-Id: Ib27ab2e0c2576b1bc81fcf937366791d3aec40c9
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 0f825f6326ab..b878fb9697d7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1482,8 +1482,6 @@ bool dc_link_setup_psr(const struct dc_link *dc_link,
 			sizeof(psr_configuration.raw));
 
 		psr_context.channel = link->ddc->ddc_pin->hw_info.ddc_channel;
-		if (psr_context.channel == 0)
-			psr_context.channel = 1;
 		psr_context.transmitterId = link->link_enc->transmitter;
 		psr_context.engineId = link->link_enc->preferred_engine;
 
-- 
2.11.0

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[PATCH v2 13/16] drm/amd/display: Fill in vrefresh and min_vblank_time for dce8/dce10

[Harry Wentland]

From: Jordan Lazare <Jordan.Lazare@amd.com>

PPLib is now calling into DC to get vrefresh and min_vblank_time, but
since full bandwidth calcs are missing for those generations, the pplib
structures were never being filled. This change fills the currently
required fields to prevent screen corruption.

Change-Id: I5438407f2e3b85f108daa3dd52afd11f702dff84
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
---
 .../drm/amd/display/dc/dce100/dce100_hw_sequencer.c | 21 +++++++++++++++++++++
 .../drm/amd/display/dc/dce100/dce100_hw_sequencer.h |  5 +++++
 .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c |  8 ++++----
 .../drm/amd/display/dc/dce110/dce110_hw_sequencer.h |  8 ++++++++
 .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c   |  2 ++
 5 files changed, 40 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
index bd8e19f1038b..f11044e0245c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
@@ -104,6 +104,26 @@ static bool dce100_enable_display_power_gating(
 		return false;
 }
 
+void dce100_pplib_apply_display_requirements(
+	struct core_dc *dc,
+	struct validate_context *context)
+{
+	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
+
+	pp_display_cfg->avail_mclk_switch_time_us =
+						dce110_get_min_vblank_time_us(context);
+
+	dce110_fill_display_configs(context, pp_display_cfg);
+
+	if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
+			struct dm_pp_display_configuration)) !=  0)
+		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
+
+	dc->prev_display_config = *pp_display_cfg;
+}
+
+
+
 static void set_displaymarks(
 		const struct core_dc *dc, struct validate_context *context)
 {
@@ -116,6 +136,7 @@ static void set_bandwidth(
 		bool decrease_allowed)
 {
 	dc->hwss.set_displaymarks(dc, context);
+	dce100_pplib_apply_display_requirements(dc, context);
 }
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
index cf497ea605c8..f51d04a66a49 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
@@ -29,8 +29,13 @@
 #include "core_types.h"
 
 struct core_dc;
+struct validate_context;
 
 bool dce100_hw_sequencer_construct(struct core_dc *dc);
 
+void dce100_pplib_apply_display_requirements(
+	struct core_dc *dc,
+	struct validate_context *context);
+
 #endif /* __DC_HWSS_DCE100_H__ */
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 2a3a39e31717..839c34409c63 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2097,7 +2097,7 @@ static void init_hw(struct core_dc *dc)
 	}
 }
 
-static void fill_display_configs(
+void dce110_fill_display_configs(
 	const struct validate_context *context,
 	struct dm_pp_display_configuration *pp_display_cfg)
 {
@@ -2146,7 +2146,7 @@ static void fill_display_configs(
 	pp_display_cfg->display_count = num_cfgs;
 }
 
-static uint32_t get_min_vblank_time_us(const struct validate_context *context)
+uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context)
 {
 	uint8_t j;
 	uint32_t min_vertical_blank_time = -1;
@@ -2224,13 +2224,13 @@ static void pplib_apply_display_requirements(
 			= context->bw_results.required_sclk_deep_sleep;
 
 	pp_display_cfg->avail_mclk_switch_time_us =
-						get_min_vblank_time_us(context);
+						dce110_get_min_vblank_time_us(context);
 	/* TODO: dce11.2*/
 	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
 
 	pp_display_cfg->disp_clk_khz = context->dispclk_khz;
 
-	fill_display_configs(context, pp_display_cfg);
+	dce110_fill_display_configs(context, pp_display_cfg);
 
 	/* TODO: is this still applicable?*/
 	if (pp_display_cfg->display_count == 1) {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
index a6b4d0d2429f..52462c17b2e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
@@ -30,6 +30,8 @@
 
 #define GAMMA_HW_POINTS_NUM 256
 struct core_dc;
+struct validate_context;
+struct dm_pp_display_configuration;
 
 bool dce110_hw_sequencer_construct(struct core_dc *dc);
 
@@ -58,5 +60,11 @@ void dce110_power_down(struct core_dc *dc);
 
 void dce110_update_pending_status(struct pipe_ctx *pipe_ctx);
 
+void dce110_fill_display_configs(
+	const struct validate_context *context,
+	struct dm_pp_display_configuration *pp_display_cfg);
+
+uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context);
+
 #endif /* __DC_HWSS_DCE110_H__ */
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
index 85a54d963f8d..9d4e7d8b836e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
@@ -31,6 +31,7 @@
 
 #include "dce/dce_hwseq.h"
 #include "dce110/dce110_hw_sequencer.h"
+#include "dce100/dce100_hw_sequencer.h"
 
 /* include DCE8 register header files */
 #include "dce/dce_8_0_d.h"
@@ -118,6 +119,7 @@ static void set_bandwidth(
 		bool decrease_allowed)
 {
 	dc->hwss.set_displaymarks(dc, context);
+	dce100_pplib_apply_display_requirements(dc, context);
 }
 
 
-- 
2.11.0

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[PATCH v2 14/16] drm/amd/display: Ignore visible flag when check surface update type.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

Change-Id: Ia80af0d7f3a1232097b87f907391a1162e4f2880
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 40a800155fe6..9a3507e743cf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1046,10 +1046,10 @@ static enum surface_update_type get_plane_info_update_type(
 	temp_plane_info.rotation = u->surface->rotation;
 	temp_plane_info.stereo_format = u->surface->stereo_format;
 	temp_plane_info.tiling_info = u->surface->tiling_info;
-	temp_plane_info.visible = u->surface->visible;
 
 	/* Special Validation parameters */
 	temp_plane_info.format = u->plane_info->format;
+	temp_plane_info.visible = u->plane_info->visible;
 
 	if (memcmp(u->plane_info, &temp_plane_info,
 			sizeof(struct dc_plane_info)) != 0)
-- 
2.11.0

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[PATCH v2 15/16] drm/amd/display: Log clock source in error condition

[Harry Wentland]

From: Jordan Lazare <Jordan.Lazare@amd.com>

Change-Id: I6a787162d9ef57471743e786c6d9f3b8b8dc273e
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index 17cdd70a2c27..34c18712970c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -187,6 +187,7 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
 			REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
 					PIXEL_RATE_PLL_SOURCE, 1);
 	} else {
-		DC_ERR("unknown clock source");
+		DC_ERR("Unknown clock source. clk_src id: %d, TG_inst: %d",
+		       clk_src->id, tg_inst);
 	}
 }
-- 
2.11.0

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[PATCH v2 16/16] drm/amd/display: Fix s3 hang on resume.

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

Avoid enabling CRTC_VERTICAL_INTERRUPT0 twice on resume.
It's enabled once from within manage_dm_interrupts in mode set
and another explicitly from amdgpu_dm_irq_resume_late.
Seems it lead to CRTC hang.

Change-Id: I7d7f29adb0f204fd6b1b2a9b36111cd2cf5bf820
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c     |  2 +-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 16 +++++++++++-----
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h |  2 +-
 3 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b3a9a9058c4a..62be159b1ea5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -581,7 +581,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
 
 	ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
 
-	amdgpu_dm_irq_resume(adev);
+	amdgpu_dm_irq_resume_late(adev);
 
 	return ret;
 }
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 682e9c3ad8e5..4aee146a848f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -504,8 +504,11 @@ int amdgpu_dm_irq_suspend(
 
 	DRM_DEBUG_KMS("DM_IRQ: suspend\n");
 
-	/* disable HW interrupt */
-	for (src = DC_IRQ_SOURCE_HPD1; src < DAL_IRQ_SOURCES_NUMBER; src++) {
+	/**
+	 * Disable HW interrupt  for HPD and HPDRX only since FLIP and VBLANK
+	 * will be disabled from manage_dm_interrupts on disable CRTC.
+	 */
+	for (src = DC_IRQ_SOURCE_HPD1; src < DC_IRQ_SOURCE_HPD6RX; src++) {
 		hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
 		hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
 		if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
@@ -544,7 +547,7 @@ int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)
 	return 0;
 }
 
-int amdgpu_dm_irq_resume(struct amdgpu_device *adev)
+int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)
 {
 	int src;
 	struct list_head *hnd_list_h, *hnd_list_l;
@@ -554,8 +557,11 @@ int amdgpu_dm_irq_resume(struct amdgpu_device *adev)
 
 	DRM_DEBUG_KMS("DM_IRQ: resume\n");
 
-	/* re-enable HW interrupt */
-	for (src = DC_IRQ_SOURCE_HPD1; src < DAL_IRQ_SOURCES_NUMBER; src++) {
+	/**
+	 * Renable HW interrupt  for HPD and only since FLIP and VBLANK
+	 * will be enabled from manage_dm_interrupts on enable CRTC.
+	 */
+	for (src = DC_IRQ_SOURCE_HPD1; src < DC_IRQ_SOURCE_HPD6; src++) {
 		hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
 		hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
 		if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h
index 9339861c8897..9d3007634266 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h
@@ -117,6 +117,6 @@ int amdgpu_dm_irq_suspend(struct amdgpu_device *adev);
  *
  */
 int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev);
-int amdgpu_dm_irq_resume(struct amdgpu_device *adev);
+int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev);
 
 #endif /* __AMDGPU_DM_IRQ_H__ */
-- 
2.11.0

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