From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH] drm/i915/glk: limit pixel clock to 99% of
 cdclk workaround
Date: Tue, 4 Apr 2017 14:39:14 +0300
Message-ID: <20170404113914.GN30290@intel.com>
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To: "Chauhan, Madhav" <madhav.chauhan@intel.com>
Cc: "Nikula, Jani" <jani.nikula@intel.com>, "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
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