From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from omzsmtpe01.verizonbusiness.com ([199.249.25.210]:29999 "EHLO omzsmtpe01.verizonbusiness.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754486AbdDDTdB (ORCPT ); Tue, 4 Apr 2017 15:33:01 -0400 From: alexander.levin@verizon.com To: "gregkh@linuxfoundation.org" CC: "stable@vger.kernel.org" Subject: [PATCH for 4.9 17/98] x86/intel_idle: Add CPU model 0x4a (Atom Z34xx series) Date: Tue, 4 Apr 2017 19:32:08 +0000 Message-ID: <20170404193158.19041-18-alexander.levin@verizon.com> References: <20170404193158.19041-1-alexander.levin@verizon.com> In-Reply-To: <20170404193158.19041-1-alexander.levin@verizon.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org List-ID: From: Andy Shevchenko [ Upstream commit 5e7ec268fd48d63cfd0e3a9be6c6443f01673bd4 ] Add CPU ID for Atom Z34xx processors. Datasheets indicate support for this, detailed information about potential quirks or limitations are missing, tho= ugh. So we just reuse the definition from official BSP code. Signed-off-by: Andy Shevchenko Signed-off-by: Len Brown Signed-off-by: Sasha Levin --- drivers/idle/intel_idle.c | 49 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 49 insertions(+) diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index 4466a2f..5ded9b2 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -724,6 +724,50 @@ static struct cpuidle_state atom_cstates[] =3D { { .enter =3D NULL } }; +static struct cpuidle_state tangier_cstates[] =3D { + { + .name =3D "C1-TNG", + .desc =3D "MWAIT 0x00", + .flags =3D MWAIT2flg(0x00), + .exit_latency =3D 1, + .target_residency =3D 4, + .enter =3D &intel_idle, + .enter_freeze =3D intel_idle_freeze, }, + { + .name =3D "C4-TNG", + .desc =3D "MWAIT 0x30", + .flags =3D MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency =3D 100, + .target_residency =3D 400, + .enter =3D &intel_idle, + .enter_freeze =3D intel_idle_freeze, }, + { + .name =3D "C6-TNG", + .desc =3D "MWAIT 0x52", + .flags =3D MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency =3D 140, + .target_residency =3D 560, + .enter =3D &intel_idle, + .enter_freeze =3D intel_idle_freeze, }, + { + .name =3D "C7-TNG", + .desc =3D "MWAIT 0x60", + .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency =3D 1200, + .target_residency =3D 4000, + .enter =3D &intel_idle, + .enter_freeze =3D intel_idle_freeze, }, + { + .name =3D "C9-TNG", + .desc =3D "MWAIT 0x64", + .flags =3D MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency =3D 10000, + .target_residency =3D 20000, + .enter =3D &intel_idle, + .enter_freeze =3D intel_idle_freeze, }, + { + .enter =3D NULL } +}; static struct cpuidle_state avn_cstates[] =3D { { .name =3D "C1-AVN", @@ -978,6 +1022,10 @@ static const struct idle_cpu idle_cpu_atom =3D { .state_table =3D atom_cstates, }; =20 +static const struct idle_cpu idle_cpu_tangier =3D { + .state_table =3D tangier_cstates, +}; + static const struct idle_cpu idle_cpu_lincroft =3D { .state_table =3D atom_cstates, .auto_demotion_disable_flags =3D ATM_LNC_C6_AUTO_DEMOTE, @@ -1066,6 +1114,7 @@ static const struct x86_cpu_id intel_idle_ids[] __ini= tconst =3D { ICPU(INTEL_FAM6_SANDYBRIDGE_X, idle_cpu_snb), ICPU(INTEL_FAM6_ATOM_CEDARVIEW, idle_cpu_atom), ICPU(INTEL_FAM6_ATOM_SILVERMONT1, idle_cpu_byt), + ICPU(INTEL_FAM6_ATOM_MERRIFIELD, idle_cpu_tangier), ICPU(INTEL_FAM6_ATOM_AIRMONT, idle_cpu_cht), ICPU(INTEL_FAM6_IVYBRIDGE, idle_cpu_ivb), ICPU(INTEL_FAM6_IVYBRIDGE_X, idle_cpu_ivt), --=20 2.9.3