From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from omzsmtpe02.verizonbusiness.com ([199.249.25.209]:4415 "EHLO omzsmtpe02.verizonbusiness.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754258AbdDDTd5 (ORCPT ); Tue, 4 Apr 2017 15:33:57 -0400 From: alexander.levin@verizon.com To: "gregkh@linuxfoundation.org" CC: "stable@vger.kernel.org" Subject: [PATCH for 4.9 64/98] PCI: Add ACS quirk for Intel Union Point Date: Tue, 4 Apr 2017 19:32:26 +0000 Message-ID: <20170404193158.19041-65-alexander.levin@verizon.com> References: <20170404193158.19041-1-alexander.levin@verizon.com> In-Reply-To: <20170404193158.19041-1-alexander.levin@verizon.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org List-ID: From: Alex Williamson [ Upstream commit 7184f5b451cf3dc61de79091d235b5d2bba2782d ] Intel 200-series chipsets have the same errata as 100-series: the ACS capability doesn't follow the PCIe spec, the capability and control registers are dwords rather than words. Add PCIe root port device IDs to existing quirk. Signed-off-by: Alex Williamson Signed-off-by: Bjorn Helgaas Signed-off-by: Sasha Levin --- drivers/pci/quirks.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 585131a..19a35fa 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4151,15 +4151,35 @@ static int pci_quirk_intel_pch_acs(struct pci_dev *= dev, u16 acs_flags) * * N.B. This doesn't fix what lspci shows. * + * The 100 series chipset specification update includes this as errata #23= [3]. + * + * The 200 series chipset (Union Point) has the same bug according to the + * specification update (Intel 200 Series Chipset Family Platform Controll= er + * Hub, Specification Update, January 2017, Revision 001, Document# 335194= -001, + * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this + * chipset include: + * + * 0xa290-0xa29f PCI Express Root port #{0-16} + * 0xa2e7-0xa2ee PCI Express Root port #{17-24} + * * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-= datasheet-vol-2.html * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-= datasheet-vol-1.html + * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-= spec-update.html + * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-= pch-spec-update.html + * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-= pch-datasheet-vol-1.html */ static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) { - return pci_is_pcie(dev) && - pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ROOT_PORT && - ((dev->device & ~0xf) =3D=3D 0xa110 || - (dev->device >=3D 0xa167 && dev->device <=3D 0xa16a)); + if (!pci_is_pcie(dev) || pci_pcie_type(dev) !=3D PCI_EXP_TYPE_ROOT_PORT) + return false; + + switch (dev->device) { + case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ + case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ + return true; + } + + return false; } =20 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) --=20 2.9.3