From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from omzsmtpe03.verizonbusiness.com ([199.249.25.208]:14342 "EHLO omzsmtpe03.verizonbusiness.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932311AbdDDTfN (ORCPT ); Tue, 4 Apr 2017 15:35:13 -0400 From: alexander.levin@verizon.com To: "gregkh@linuxfoundation.org" CC: "stable@vger.kernel.org" Subject: [PATCH for 4.9 98/98] can: flexcan: add quirk FLEXCAN_QUIRK_ENABLE_EACEN_RRS Date: Tue, 4 Apr 2017 19:32:39 +0000 Message-ID: <20170404193158.19041-99-alexander.levin@verizon.com> References: <20170404193158.19041-1-alexander.levin@verizon.com> In-Reply-To: <20170404193158.19041-1-alexander.levin@verizon.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org List-ID: From: Marc Kleine-Budde [ Upstream commit 9eb7aa891101a4a09114ff3191f9877ea35eae06 ] In order to receive RTR frames in the non HW FIFO mode the RSS and EACEN bi= ts of the reg_ctrl2 have to be activated. As this has no side effect in the FI= FO mode, we do this unconditionally on cores with the reg_ctrl2. Signed-off-by: Marc Kleine-Budde Signed-off-by: Sasha Levin --- drivers/net/can/flexcan.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c index 16f7cad..5884ca7 100644 --- a/drivers/net/can/flexcan.c +++ b/drivers/net/can/flexcan.c @@ -189,7 +189,8 @@ */ #define FLEXCAN_QUIRK_BROKEN_ERR_STATE BIT(1) /* [TR]WRN_INT not connected= */ #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask *= / -#define FLEXCAN_QUIRK_DISABLE_MECR BIT(3) /* Disble Memory error detection= */ +#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit = in ctrl2 */ +#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disble Memory error detection= */ =20 /* Structure of the message buffer */ struct flexcan_mb { @@ -268,12 +269,13 @@ static struct flexcan_devtype_data fsl_p1010_devtype_= data =3D { =20 static struct flexcan_devtype_data fsl_imx28_devtype_data; =20 -static struct flexcan_devtype_data fsl_imx6q_devtype_data =3D { - .quirks =3D FLEXCAN_QUIRK_DISABLE_RXFG, +static const struct flexcan_devtype_data fsl_imx6q_devtype_data =3D { + .quirks =3D FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS, }; =20 -static struct flexcan_devtype_data fsl_vf610_devtype_data =3D { - .quirks =3D FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR, +static const struct flexcan_devtype_data fsl_vf610_devtype_data =3D { + .quirks =3D FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | + FLEXCAN_QUIRK_DISABLE_MECR, }; =20 static const struct can_bittiming_const flexcan_bittiming_const =3D { @@ -883,6 +885,12 @@ static int flexcan_chip_start(struct net_device *dev) netdev_dbg(dev, "%s: writing ctrl=3D0x%08x", __func__, reg_ctrl); flexcan_write(reg_ctrl, ®s->ctrl); =20 + if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) { + reg_ctrl2 =3D flexcan_read(®s->ctrl2); + reg_ctrl2 |=3D FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS; + flexcan_write(reg_ctrl2, ®s->ctrl2); + } + /* clear and invalidate all mailboxes first */ for (i =3D FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->mb); i++) { flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE, --=20 2.9.3