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From: Andres Rodriguez <andresx7-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: andresx7-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Subject: [PATCH 24/25] drm/amdgpu: guarantee bijective mapping of ring ids for LRU v3
Date: Tue,  4 Apr 2017 18:05:50 -0400	[thread overview]
Message-ID: <20170404220551.8669-25-andresx7@gmail.com> (raw)
In-Reply-To: <20170404220551.8669-1-andresx7-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Depending on usage patterns, the current LRU policy may create a
non-injective mapping between userspace ring ids and kernel rings.

This behaviour is undesired as apps that attempt to fill all HW blocks
would be unable to reach some of them.

This change forces the LRU policy to create bijective mappings only.

v2: compress ring_blacklist
v3: simplify amdgpu_ring_is_blacklisted() logic

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c | 16 +++++++++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c      | 33 +++++++++++++++++++++------
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h      |  4 ++--
 3 files changed, 42 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
index 054d750..5a7c691 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
@@ -108,24 +108,36 @@ static enum amdgpu_ring_type amdgpu_hw_ip_to_ring_type(int hw_ip)
 		DRM_ERROR("Invalid HW IP specified %d\n", hw_ip);
 		return -1;
 	}
 }
 
 static int amdgpu_lru_map(struct amdgpu_device *adev,
 			  struct amdgpu_queue_mapper *mapper,
 			  int user_ring,
 			  struct amdgpu_ring **out_ring)
 {
-	int r;
+	int r, i, j;
 	int ring_type = amdgpu_hw_ip_to_ring_type(mapper->hw_ip);
+	int ring_blacklist[AMDGPU_MAX_RINGS];
+	struct amdgpu_ring *ring;
 
-	r = amdgpu_ring_lru_get(adev, ring_type, out_ring);
+	/* 0 is a valid ring index, so initialize to -1 */
+	memset(ring_blacklist, 0xff, sizeof(ring_blacklist));
+
+	for (i = 0, j = 0; i < AMDGPU_MAX_RINGS; i++) {
+		ring = mapper->queue_map[i];
+		if (ring)
+			ring_blacklist[j++] = ring->idx;
+	}
+
+	r = amdgpu_ring_lru_get(adev, ring_type, ring_blacklist,
+				j, out_ring);
 	if (r)
 		return r;
 
 	return amdgpu_update_cached_map(mapper, user_ring, *out_ring);
 }
 
 /**
  * amdgpu_queue_mgr_init - init an amdgpu_queue_mgr struct
  *
  * @adev: amdgpu_device pointer
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index b1af952..09fa8f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -419,46 +419,65 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)
 	ring->adev->rings[ring->idx] = NULL;
 }
 
 static void amdgpu_ring_lru_touch_locked(struct amdgpu_device *adev,
 					 struct amdgpu_ring *ring)
 {
 	/* list_move_tail handles the case where ring isn't part of the list */
 	list_move_tail(&ring->lru_list, &adev->ring_lru_list);
 }
 
+static bool amdgpu_ring_is_blacklisted(struct amdgpu_ring *ring,
+				       int *blacklist, int num_blacklist)
+{
+	int i;
+
+	for (i = 0; i < num_blacklist; i++) {
+		if (ring->idx == blacklist[i])
+			return true;
+	}
+
+	return false;
+}
+
 /**
  * amdgpu_ring_lru_get - get the least recently used ring for a HW IP block
  *
  * @adev: amdgpu_device pointer
  * @type: amdgpu_ring_type enum
+ * @blacklist: blacklisted ring ids array
+ * @num_blacklist: number of entries in @blacklist
  * @ring: output ring
  *
  * Retrieve the amdgpu_ring structure for the least recently used ring of
  * a specific IP block (all asics).
  * Returns 0 on success, error on failure.
  */
-int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
-			struct amdgpu_ring **ring)
+int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, int *blacklist,
+			int num_blacklist, struct amdgpu_ring **ring)
 {
 	struct amdgpu_ring *entry;
 
 	/* List is sorted in LRU order, find first entry corresponding
 	 * to the desired HW IP */
 	*ring = NULL;
 	spin_lock(&adev->ring_lru_list_lock);
 	list_for_each_entry(entry, &adev->ring_lru_list, lru_list) {
-		if (entry->funcs->type == type) {
-			*ring = entry;
-			amdgpu_ring_lru_touch_locked(adev, *ring);
-			break;
-		}
+		if (entry->funcs->type != type)
+			continue;
+
+		if (amdgpu_ring_is_blacklisted(entry, blacklist, num_blacklist))
+			continue;
+
+		*ring = entry;
+		amdgpu_ring_lru_touch_locked(adev, *ring);
+		break;
 	}
 	spin_unlock(&adev->ring_lru_list_lock);
 
 	if (!*ring) {
 		DRM_ERROR("Ring LRU contains no entries for ring type:%d\n", type);
 		return -EINVAL;
 	}
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index e8ba708..2de56f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -203,22 +203,22 @@ void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
 void amdgpu_ring_commit(struct amdgpu_ring *ring);
 void amdgpu_ring_undo(struct amdgpu_ring *ring);
 int amdgpu_ring_priority_get(struct amdgpu_ring *ring,
 			     enum amd_sched_priority priority);
 void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
 			      enum amd_sched_priority priority);
 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 		     unsigned ring_size, struct amdgpu_irq_src *irq_src,
 		     unsigned irq_type);
 void amdgpu_ring_fini(struct amdgpu_ring *ring);
-int amdgpu_ring_lru_get(struct amdgpu_device *adev, int hw_ip,
-			struct amdgpu_ring **ring);
+int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, int *blacklist,
+			int num_blacklist, struct amdgpu_ring **ring);
 void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring);
 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
 {
 	int i = 0;
 	while (i <= ring->buf_mask)
 		ring->ring[i++] = ring->funcs->nop;
 
 }
 
 #endif
-- 
2.9.3

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  parent reply	other threads:[~2017-04-04 22:05 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-04 22:05 [PATCH] Add support for high priority scheduling in amdgpu v7 Andres Rodriguez
     [not found] ` <20170404220551.8669-1-andresx7-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-04-04 22:05   ` [PATCH 01/25] drm/amdgpu: refactor MQD/HQD initialization v2 Andres Rodriguez
2017-04-04 22:05   ` [PATCH 02/25] drm/amdgpu: doorbell registers need only be set once v2 Andres Rodriguez
2017-04-04 22:05   ` [PATCH 03/25] drm/amdgpu: detect timeout error when deactivating hqd Andres Rodriguez
2017-04-04 22:05   ` [PATCH 04/25] drm/amdgpu: remove duplicate definition of cik_mqd Andres Rodriguez
2017-04-04 22:05   ` [PATCH 05/25] drm/amdgpu: unify MQD programming sequence for kfd and amdgpu Andres Rodriguez
2017-04-04 22:05   ` [PATCH 06/25] drm/amdgpu: rename rdev to adev Andres Rodriguez
2017-04-04 22:05   ` [PATCH 07/25] drm/amdgpu: take ownership of per-pipe configuration v2 Andres Rodriguez
2017-04-04 22:05   ` [PATCH 08/25] drm/radeon: take ownership of pipe initialization Andres Rodriguez
2017-04-04 22:05   ` [PATCH 09/25] drm/amdgpu: allow split of queues with kfd at queue granularity v2 Andres Rodriguez
     [not found]     ` <20170404220551.8669-10-andresx7-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-04-05  3:16       ` Alex Deucher
     [not found]         ` <CADnq5_PkNpqK-aKwPSFemE7oOXU0rJ38n9rtn_udWz8u+KHXjQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-04-05  4:09           ` Andres Rodriguez
2017-04-04 22:05   ` [PATCH 10/25] drm/amdgpu: teach amdgpu how to enable interrupts for any pipe v2 Andres Rodriguez
2017-04-04 22:05   ` [PATCH 11/25] drm/amdkfd: allow split HQD on per-queue granularity v4 Andres Rodriguez
2017-04-04 22:05   ` [PATCH 12/25] drm/amdgpu: remove duplicate magic constants from amdgpu_amdkfd_gfx*.c Andres Rodriguez
2017-04-04 22:05   ` [PATCH 13/25] drm/amdgpu: allocate queues horizontally across pipes Andres Rodriguez
2017-04-04 22:05   ` [PATCH 14/25] drm/amdgpu: remove hardcoded queue_mask in PACKET3_SET_RESOURCES Andres Rodriguez
2017-04-04 22:05   ` [PATCH 15/25] drm/amdgpu: new queue policy, take first 2 queues of each pipe Andres Rodriguez
2017-04-04 22:05   ` [PATCH 16/25] drm/amdgpu: untie user ring ids from kernel ring ids v4 Andres Rodriguez
     [not found]     ` <20170404220551.8669-17-andresx7-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-04-05  3:06       ` Alex Deucher
     [not found]         ` <CADnq5_MA9npTkiX0gNsPDSyz7HoeHPSBpvcuYN3Vt2D7NtwPjw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-04-05  3:12           ` Andres Rodriguez
2017-04-04 22:05   ` [PATCH 17/25] drm/amdgpu: implement lru amdgpu_queue_mgr policy for compute v4 Andres Rodriguez
2017-04-04 22:05   ` [PATCH 18/25] drm/amdgpu: add parameter to allocate high priority contexts v7 Andres Rodriguez
2017-04-04 22:05   ` [PATCH 19/25] drm/amdgpu: add framework for HW specific priority settings v6 Andres Rodriguez
2017-04-04 22:05   ` [PATCH 20/25] drm/amdgpu: convert srbm lock to a spinlock v2 Andres Rodriguez
2017-04-04 22:05   ` [PATCH 21/25] drm/amdgpu: implement ring set_priority for gfx_v8 compute v5 Andres Rodriguez
2017-04-04 22:05   ` [PATCH 22/25] drm/amdgpu: condense mqd programming sequence Andres Rodriguez
2017-04-04 22:05   ` [PATCH 23/25] drm/amdgpu: workaround tonga HW bug in HQD " Andres Rodriguez
2017-04-04 22:05   ` Andres Rodriguez [this message]
2017-04-04 22:05   ` [PATCH 25/25] drm/amdgpu: use LRU mapping policy for SDMA engines Andres Rodriguez

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