[PATCH 0/2] pmu0 MMIO region for A64 USB PHY

[PATCH 0/2] pmu0 MMIO region for A64 USB PHY

[Icenowy Zheng]

The USB PHY of A64 contains a "pmu0" MMIO region, which contains some control
registers for the EHCI0/OHCI0 pair on A64 SoC.

This pair is not used currently in 4.11, but when enabling it in 4.12, the
MMIO region is needed.

In order to prevent device tree compatibility breakage, add this region in
4.11.

Icenowy Zheng (2):
  dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
  arm64: allwinner: a64: add pmu0 regs for USB PHY

 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi           | 2 ++
 2 files changed, 3 insertions(+)

-- 
2.12.2

[PATCH 0/2] pmu0 MMIO region for A64 USB PHY

[Icenowy Zheng]

The USB PHY of A64 contains a "pmu0" MMIO region, which contains some control
registers for the EHCI0/OHCI0 pair on A64 SoC.

This pair is not used currently in 4.11, but when enabling it in 4.12, the
MMIO region is needed.

In order to prevent device tree compatibility breakage, add this region in
4.11.

Icenowy Zheng (2):
  dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
  arm64: allwinner: a64: add pmu0 regs for USB PHY

 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi           | 2 ++
 2 files changed, 3 insertions(+)

-- 
2.12.2

[PATCH 0/2] pmu0 MMIO region for A64 USB PHY

[Icenowy Zheng]

The USB PHY of A64 contains a "pmu0" MMIO region, which contains some control
registers for the EHCI0/OHCI0 pair on A64 SoC.

This pair is not used currently in 4.11, but when enabling it in 4.12, the
MMIO region is needed.

In order to prevent device tree compatibility breakage, add this region in
4.11.

Icenowy Zheng (2):
  dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
  arm64: allwinner: a64: add pmu0 regs for USB PHY

 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi           | 2 ++
 2 files changed, 3 insertions(+)

-- 
2.12.2

[PATCH 1/2] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

[Icenowy Zheng]

From: Icenowy Zheng <icenowy@aosc.xyz>

Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
controllers: one is MUSB and the other is a EHCI/OHCI pair.

When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
tweak, like other EHCI/OHCI pairs in Allwinner SoCs.

Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index e42334258185..005bc22938ff 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -15,6 +15,7 @@ Required properties:
 - reg : a list of offset + length pairs
 - reg-names :
   * "phy_ctrl"
+  * "pmu0" for H3, V3s and A64
   * "pmu1"
   * "pmu2" for sun4i, sun6i or sun7i
 - #phy-cells : from the generic phy bindings, must be 1
-- 
2.12.2

[PATCH 1/2] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

[Icenowy Zheng]

From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>

Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
controllers: one is MUSB and the other is a EHCI/OHCI pair.

When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
tweak, like other EHCI/OHCI pairs in Allwinner SoCs.

Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
Acked-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Signed-off-by: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
---
 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index e42334258185..005bc22938ff 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -15,6 +15,7 @@ Required properties:
 - reg : a list of offset + length pairs
 - reg-names :
   * "phy_ctrl"
+  * "pmu0" for H3, V3s and A64
   * "pmu1"
   * "pmu2" for sun4i, sun6i or sun7i
 - #phy-cells : from the generic phy bindings, must be 1
-- 
2.12.2

[PATCH 1/2] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

[Icenowy Zheng]

From: Icenowy Zheng <icenowy@aosc.xyz>

Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
controllers: one is MUSB and the other is a EHCI/OHCI pair.

When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
tweak, like other EHCI/OHCI pairs in Allwinner SoCs.

Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index e42334258185..005bc22938ff 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -15,6 +15,7 @@ Required properties:
 - reg : a list of offset + length pairs
 - reg-names :
   * "phy_ctrl"
+  * "pmu0" for H3, V3s and A64
   * "pmu1"
   * "pmu2" for sun4i, sun6i or sun7i
 - #phy-cells : from the generic phy bindings, must be 1
-- 
2.12.2

[PATCH 2/2] arm64: allwinner: a64: add pmu0 regs for USB PHY

[Icenowy Zheng]

The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI
controller pair that can be connected to the PHY0.

Add the MMIO region for PHY node.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1c64ea2d23f9..0565779e66fa 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -179,8 +179,10 @@
 		usbphy: phy@01c19400 {
 			compatible = "allwinner,sun50i-a64-usb-phy";
 			reg = <0x01c19400 0x14>,
+			      <0x01c1a800 0x4>,
 			      <0x01c1b800 0x4>;
 			reg-names = "phy_ctrl",
+				    "pmu0",
 				    "pmu1";
 			clocks = <&ccu CLK_USB_PHY0>,
 				 <&ccu CLK_USB_PHY1>;
-- 
2.12.2

[PATCH 2/2] arm64: allwinner: a64: add pmu0 regs for USB PHY

[Icenowy Zheng]

The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI
controller pair that can be connected to the PHY0.

Add the MMIO region for PHY node.

Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1c64ea2d23f9..0565779e66fa 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -179,8 +179,10 @@
 		usbphy: phy@01c19400 {
 			compatible = "allwinner,sun50i-a64-usb-phy";
 			reg = <0x01c19400 0x14>,
+			      <0x01c1a800 0x4>,
 			      <0x01c1b800 0x4>;
 			reg-names = "phy_ctrl",
+				    "pmu0",
 				    "pmu1";
 			clocks = <&ccu CLK_USB_PHY0>,
 				 <&ccu CLK_USB_PHY1>;
-- 
2.12.2

[PATCH 2/2] arm64: allwinner: a64: add pmu0 regs for USB PHY

[Icenowy Zheng]

The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI
controller pair that can be connected to the PHY0.

Add the MMIO region for PHY node.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1c64ea2d23f9..0565779e66fa 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -179,8 +179,10 @@
 		usbphy: phy at 01c19400 {
 			compatible = "allwinner,sun50i-a64-usb-phy";
 			reg = <0x01c19400 0x14>,
+			      <0x01c1a800 0x4>,
 			      <0x01c1b800 0x4>;
 			reg-names = "phy_ctrl",
+				    "pmu0",
 				    "pmu1";
 			clocks = <&ccu CLK_USB_PHY0>,
 				 <&ccu CLK_USB_PHY1>;
-- 
2.12.2

Re: [PATCH 2/2] arm64: allwinner: a64: add pmu0 regs for USB PHY

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 416 bytes --]

On Wed, Apr 05, 2017 at 10:30:34PM +0800, Icenowy Zheng wrote:
> The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI
> controller pair that can be connected to the PHY0.
> 
> Add the MMIO region for PHY node.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Applied, thanks
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 2/2] arm64: allwinner: a64: add pmu0 regs for USB PHY

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 421 bytes --]

On Wed, Apr 05, 2017 at 10:30:34PM +0800, Icenowy Zheng wrote:
> The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI
> controller pair that can be connected to the PHY0.
> 
> Add the MMIO region for PHY node.
> 
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>

Applied, thanks
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[PATCH 2/2] arm64: allwinner: a64: add pmu0 regs for USB PHY

[Maxime Ripard]

On Wed, Apr 05, 2017 at 10:30:34PM +0800, Icenowy Zheng wrote:
> The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI
> controller pair that can be connected to the PHY0.
> 
> Add the MMIO region for PHY node.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Applied, thanks
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Re: [PATCH 0/2] pmu0 MMIO region for A64 USB PHY

[Kishon Vijay Abraham I]

Hi,

On Wednesday 05 April 2017 08:00 PM, Icenowy Zheng wrote:
> The USB PHY of A64 contains a "pmu0" MMIO region, which contains some control
> registers for the EHCI0/OHCI0 pair on A64 SoC.
> 
> This pair is not used currently in 4.11, but when enabling it in 4.12, the
> MMIO region is needed.
> 
> In order to prevent device tree compatibility breakage, add this region in
> 4.11.

I feel the binding documentation can go along with the dt changes. Moreover I
have no plans of sending another pull request for this -rc cycle.

FWIW:
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

Thanks
Kishon
> 
> Icenowy Zheng (2):
>   dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
>   arm64: allwinner: a64: add pmu0 regs for USB PHY
> 
>  Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi           | 2 ++
>  2 files changed, 3 insertions(+)
> 

Re: [PATCH 0/2] pmu0 MMIO region for A64 USB PHY

[Kishon Vijay Abraham I]

Hi,

On Wednesday 05 April 2017 08:00 PM, Icenowy Zheng wrote:
> The USB PHY of A64 contains a "pmu0" MMIO region, which contains some control
> registers for the EHCI0/OHCI0 pair on A64 SoC.
> 
> This pair is not used currently in 4.11, but when enabling it in 4.12, the
> MMIO region is needed.
> 
> In order to prevent device tree compatibility breakage, add this region in
> 4.11.

I feel the binding documentation can go along with the dt changes. Moreover I
have no plans of sending another pull request for this -rc cycle.

FWIW:
Acked-by: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>

Thanks
Kishon
> 
> Icenowy Zheng (2):
>   dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
>   arm64: allwinner: a64: add pmu0 regs for USB PHY
> 
>  Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi           | 2 ++
>  2 files changed, 3 insertions(+)
> 

[PATCH 0/2] pmu0 MMIO region for A64 USB PHY

[Kishon Vijay Abraham I]

Hi,

On Wednesday 05 April 2017 08:00 PM, Icenowy Zheng wrote:
> The USB PHY of A64 contains a "pmu0" MMIO region, which contains some control
> registers for the EHCI0/OHCI0 pair on A64 SoC.
> 
> This pair is not used currently in 4.11, but when enabling it in 4.12, the
> MMIO region is needed.
> 
> In order to prevent device tree compatibility breakage, add this region in
> 4.11.

I feel the binding documentation can go along with the dt changes. Moreover I
have no plans of sending another pull request for this -rc cycle.

FWIW:
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

Thanks
Kishon
> 
> Icenowy Zheng (2):
>   dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
>   arm64: allwinner: a64: add pmu0 regs for USB PHY
> 
>  Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi           | 2 ++
>  2 files changed, 3 insertions(+)
>