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From: Qi Zhang <qi.z.zhang@intel.com>
To: jingjing.wu@intel.com, helin.zhang@intel.com
Cc: ferruh.yigit@intel.com, jianbo.liu@linaro.org,
	chaozhu@linux.vnet.ibm.com, dev@dpdk.org,
	Qi Zhang <qi.z.zhang@intel.com>
Subject: [PATCH v8 2/3] net/i40e: configurable PTYPE mapping
Date: Thu,  6 Apr 2017 23:25:04 -0400	[thread overview]
Message-ID: <20170407032505.61691-3-qi.z.zhang@intel.com> (raw)
In-Reply-To: <20170407032505.61691-1-qi.z.zhang@intel.com>

The patch adds 4 APIs to support configurable
PTYPE mapping for i40e device.
rte_pmd_i40e_ptype_mapping_get.
rte_pmd_i40e_ptype_mapping_replace.
rte_pmd_i40e_ptype_mapping_reset.
rte_pmd_i40e_ptype_mapping_update.
The mapping from hardware defined packet type to software defined packet
type can be updated/reset/read out with these APIs.
Also a software ptype with the most significent bit set will be regarded
as a user defined ptype (RTE_PMD_I40E_PTYPE_USER_DEFINE_MASK) so
application can use it to defined its own PTYPE naming system.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---

v5:

- Rebase to dpdk-next-net

v4:

- Add comment to explain the "user defined" ptype.

v2:

- Rename APIs to rte_pmd_i40e_ptype_mapping_xxx

- Add missing API declaration in rte_pmd_i40e_version.map

- Add missing PTYPE in check_invalid_pkt_type

- Fix couple typo error

 drivers/net/i40e/i40e_ethdev.c            | 229 ++++++++++++++++++++++++++++++
 drivers/net/i40e/rte_pmd_i40e.h           |  86 +++++++++++
 drivers/net/i40e/rte_pmd_i40e_version.map |   4 +
 3 files changed, 319 insertions(+)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 2b95996..7ba9bed 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -12469,3 +12469,232 @@ i40e_init_log(void)
 	if (i40e_logtype_driver >= 0)
 		rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
 }
+
+static int check_invalid_pkt_type(uint32_t pkt_type)
+{
+	uint32_t l2, l3, l4, tnl, il2, il3, il4;
+
+	l2 = pkt_type & RTE_PTYPE_L2_MASK;
+	l3 = pkt_type & RTE_PTYPE_L3_MASK;
+	l4 = pkt_type & RTE_PTYPE_L4_MASK;
+	tnl = pkt_type & RTE_PTYPE_TUNNEL_MASK;
+	il2 = pkt_type & RTE_PTYPE_INNER_L2_MASK;
+	il3 = pkt_type & RTE_PTYPE_INNER_L3_MASK;
+	il4 = pkt_type & RTE_PTYPE_INNER_L4_MASK;
+
+	if (l2 &&
+	    l2 != RTE_PTYPE_L2_ETHER &&
+	    l2 != RTE_PTYPE_L2_ETHER_TIMESYNC &&
+	    l2 != RTE_PTYPE_L2_ETHER_ARP &&
+	    l2 != RTE_PTYPE_L2_ETHER_LLDP &&
+	    l2 != RTE_PTYPE_L2_ETHER_NSH &&
+	    l2 != RTE_PTYPE_L2_ETHER_VLAN &&
+	    l2 != RTE_PTYPE_L2_ETHER_QINQ)
+		return -1;
+
+	if (l3 &&
+	    l3 != RTE_PTYPE_L3_IPV4 &&
+	    l3 != RTE_PTYPE_L3_IPV4_EXT &&
+	    l3 != RTE_PTYPE_L3_IPV6 &&
+	    l3 != RTE_PTYPE_L3_IPV4_EXT_UNKNOWN &&
+	    l3 != RTE_PTYPE_L3_IPV6_EXT &&
+	    l3 != RTE_PTYPE_L3_IPV6_EXT_UNKNOWN)
+		return -1;
+
+	if (l4 &&
+	    l4 != RTE_PTYPE_L4_TCP &&
+	    l4 != RTE_PTYPE_L4_UDP &&
+	    l4 != RTE_PTYPE_L4_FRAG &&
+	    l4 != RTE_PTYPE_L4_SCTP &&
+	    l4 != RTE_PTYPE_L4_ICMP &&
+	    l4 != RTE_PTYPE_L4_NONFRAG)
+		return -1;
+
+	if (tnl &&
+	    tnl != RTE_PTYPE_TUNNEL_IP &&
+	    tnl != RTE_PTYPE_TUNNEL_GRENAT &&
+	    tnl != RTE_PTYPE_TUNNEL_VXLAN &&
+	    tnl != RTE_PTYPE_TUNNEL_NVGRE &&
+	    tnl != RTE_PTYPE_TUNNEL_GENEVE &&
+	    tnl != RTE_PTYPE_TUNNEL_GRENAT)
+		return -1;
+
+	if (il2 &&
+	    il2 != RTE_PTYPE_INNER_L2_ETHER &&
+	    il2 != RTE_PTYPE_INNER_L2_ETHER_VLAN &&
+	    il2 != RTE_PTYPE_INNER_L2_ETHER_QINQ)
+		return -1;
+
+	if (il3 &&
+	    il3 != RTE_PTYPE_INNER_L3_IPV4 &&
+	    il3 != RTE_PTYPE_INNER_L3_IPV4_EXT &&
+	    il3 != RTE_PTYPE_INNER_L3_IPV6 &&
+	    il3 != RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN &&
+	    il3 != RTE_PTYPE_INNER_L3_IPV6_EXT &&
+	    il3 != RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN)
+		return -1;
+
+	if (il4 &&
+	    il4 != RTE_PTYPE_INNER_L4_TCP &&
+	    il4 != RTE_PTYPE_INNER_L4_UDP &&
+	    il4 != RTE_PTYPE_INNER_L4_FRAG &&
+	    il4 != RTE_PTYPE_INNER_L4_SCTP &&
+	    il4 != RTE_PTYPE_INNER_L4_ICMP &&
+	    il4 != RTE_PTYPE_INNER_L4_NONFRAG)
+		return -1;
+
+	return 0;
+}
+
+static int check_invalid_ptype_mapping(
+		struct rte_pmd_i40e_ptype_mapping *mapping_table,
+		uint16_t count)
+{
+	int i;
+
+	for (i = 0; i < count; i++) {
+		uint16_t ptype = mapping_table[i].hw_ptype;
+		uint32_t pkt_type = mapping_table[i].sw_ptype;
+
+		if (ptype >= I40E_MAX_PKT_TYPE)
+			return -1;
+
+		if (pkt_type == RTE_PTYPE_UNKNOWN)
+			continue;
+
+		if (pkt_type & RTE_PMD_I40E_PTYPE_USER_DEFINE_MASK)
+			continue;
+
+		if (check_invalid_pkt_type(pkt_type))
+			return -1;
+	}
+
+	return 0;
+}
+
+int
+rte_pmd_i40e_ptype_mapping_update(
+			uint8_t port,
+			struct rte_pmd_i40e_ptype_mapping *mapping_items,
+			uint16_t count,
+			uint8_t exclusive)
+{
+	struct rte_eth_dev *dev;
+	struct i40e_adapter *ad;
+	int i;
+
+	RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
+
+	dev = &rte_eth_devices[port];
+
+	if (!is_device_supported(dev, &rte_i40e_pmd))
+		return -ENOTSUP;
+
+	if (count > I40E_MAX_PKT_TYPE)
+		return -EINVAL;
+
+	if (check_invalid_ptype_mapping(mapping_items, count))
+		return -EINVAL;
+
+	ad = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
+
+	if (exclusive) {
+		for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
+			ad->ptype_tbl[i] = RTE_PTYPE_UNKNOWN;
+	}
+
+	for (i = 0; i < count; i++)
+		ad->ptype_tbl[mapping_items[i].hw_ptype]
+			= mapping_items[i].sw_ptype;
+
+	return 0;
+}
+
+int rte_pmd_i40e_ptype_mapping_reset(uint8_t port)
+{
+	struct rte_eth_dev *dev;
+
+	RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
+
+	dev = &rte_eth_devices[port];
+
+	if (!is_device_supported(dev, &rte_i40e_pmd))
+		return -ENOTSUP;
+
+	i40e_set_default_ptype_table(dev);
+
+	return 0;
+}
+
+int rte_pmd_i40e_ptype_mapping_get(
+			uint8_t port,
+			struct rte_pmd_i40e_ptype_mapping *mapping_items,
+			uint16_t size,
+			uint16_t *count,
+			uint8_t valid_only)
+{
+	struct rte_eth_dev *dev;
+	struct i40e_adapter *ad;
+	int n = 0;
+	uint16_t i;
+
+	RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
+
+	dev = &rte_eth_devices[port];
+
+	if (!is_device_supported(dev, &rte_i40e_pmd))
+		return -ENOTSUP;
+
+	ad = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
+
+	for (i = 0; i < I40E_MAX_PKT_TYPE; i++) {
+		if (n >= size)
+			break;
+		if (valid_only && ad->ptype_tbl[i] == RTE_PTYPE_UNKNOWN)
+			continue;
+		mapping_items[n].hw_ptype = i;
+		mapping_items[n].sw_ptype = ad->ptype_tbl[i];
+		n++;
+	}
+
+	*count = n;
+	return 0;
+}
+
+int rte_pmd_i40e_ptype_mapping_replace(uint8_t port,
+				       uint32_t target,
+				       uint8_t mask,
+				       uint32_t pkt_type)
+{
+	struct rte_eth_dev *dev;
+	struct i40e_adapter *ad;
+	uint16_t i;
+
+	RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
+
+	dev = &rte_eth_devices[port];
+
+	if (!is_device_supported(dev, &rte_i40e_pmd))
+		return -ENOTSUP;
+
+	if (!mask && check_invalid_pkt_type(target))
+		return -EINVAL;
+
+	if (check_invalid_pkt_type(pkt_type))
+		return -EINVAL;
+
+	ad = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
+
+	for (i = 0; i < I40E_MAX_PKT_TYPE; i++) {
+		if (mask) {
+			if ((target | ad->ptype_tbl[i]) == target &&
+			    (target & ad->ptype_tbl[i]))
+				ad->ptype_tbl[i] = pkt_type;
+		} else {
+			if (ad->ptype_tbl[i] == target)
+				ad->ptype_tbl[i] = pkt_type;
+		}
+	}
+
+	return 0;
+}
diff --git a/drivers/net/i40e/rte_pmd_i40e.h b/drivers/net/i40e/rte_pmd_i40e.h
index 8e15630..f7b76f7 100644
--- a/drivers/net/i40e/rte_pmd_i40e.h
+++ b/drivers/net/i40e/rte_pmd_i40e.h
@@ -107,6 +107,18 @@ struct rte_pmd_i40e_profile_list {
 };
 
 /**
+ * ptype mapping table only accept RTE_PTYPE_XXX or "user defined" ptype.
+ * A ptype with MSB set will be regarded as a user defined ptype.
+ * Below macro help to create a user defined ptype.
+ */
+#define RTE_PMD_I40E_PTYPE_USER_DEFINE_MASK 0x80000000
+
+struct rte_pmd_i40e_ptype_mapping {
+	uint16_t hw_ptype; /**< hardware defined packet type*/
+	uint32_t sw_ptype; /**< software defined packet type */
+};
+
+/**
  * Notify VF when PF link status changes.
  *
  * @param port
@@ -495,4 +507,78 @@ int rte_pmd_i40e_process_ddp_package(uint8_t port, uint8_t *buff,
  */
 int rte_pmd_i40e_get_ddp_list(uint8_t port, uint8_t *buff, uint32_t size);
 
+/**
+ * Update hardware defined ptype to software defined packet type
+ * mapping table.
+ *
+ * @param port
+ *    pointer to port identifier of the device.
+ * @param mapping_items
+ *    the base address of the mapping items array.
+ * @param count
+ *    number of mapping items.
+ * @param exclusive
+ *    the flag indicate different ptype mapping update method.
+ *    -(0) only overwrite referred PTYPE mapping,
+ *	keep other PTYPEs mapping unchanged.
+ *    -(!0) overwrite referred PTYPE mapping,
+ *	set other PTYPEs maps to PTYPE_UNKNOWN.
+ */
+int rte_pmd_i40e_ptype_mapping_update(
+			uint8_t port,
+			struct rte_pmd_i40e_ptype_mapping *mapping_items,
+			uint16_t count,
+			uint8_t exclusive);
+
+/**
+ * Reset hardware defined ptype to software defined ptype
+ * mapping table to default.
+ *
+ * @param port
+ *    pointer to port identifier of the device
+ */
+int rte_pmd_i40e_ptype_mapping_reset(uint8_t port);
+
+/**
+ * Get hardware defined ptype to software defined ptype
+ * mapping items.
+ *
+ * @param port
+ *    pointer to port identifier of the device.
+ * @param mapping_items
+ *    the base address of the array to store returned items.
+ * @param size
+ *    the size of the input array.
+ * @param count
+ *    the place to store the number of returned items.
+ * @param valid_only
+ *    -(0) return full mapping table.
+ *    -(!0) only return mapping items which packet_type != RTE_PTYPE_UNKNOWN.
+ */
+int rte_pmd_i40e_ptype_mapping_get(
+			uint8_t port,
+			struct rte_pmd_i40e_ptype_mapping *mapping_items,
+			uint16_t size,
+			uint16_t *count,
+			uint8_t valid_only);
+
+/**
+ * Replace a specific or a group of software defined ptypes
+ * with a new one
+ *
+ * @param port
+ *    pointer to port identifier of the device
+ * @param target
+ *    the packet type to be replaced
+ * @param mask
+ *    -(0) target represent a specific software defined ptype.
+ *    -(!0) target is a mask to represent a group of software defined ptypes.
+ * @param pkt_type
+ *    the new packet type to overwrite
+ */
+int rte_pmd_i40e_ptype_mapping_replace(uint8_t port,
+				       uint32_t target,
+				       uint8_t mask,
+				       uint32_t pkt_type);
+
 #endif /* _PMD_I40E_H_ */
diff --git a/drivers/net/i40e/rte_pmd_i40e_version.map b/drivers/net/i40e/rte_pmd_i40e_version.map
index dbb994e..3b0e805 100644
--- a/drivers/net/i40e/rte_pmd_i40e_version.map
+++ b/drivers/net/i40e/rte_pmd_i40e_version.map
@@ -8,6 +8,10 @@ DPDK_17.02 {
 
 	rte_pmd_i40e_get_vf_stats;
 	rte_pmd_i40e_ping_vfs;
+	rte_pmd_i40e_ptype_mapping_get;
+	rte_pmd_i40e_ptype_mapping_replace;
+	rte_pmd_i40e_ptype_mapping_reset;
+	rte_pmd_i40e_ptype_mapping_update;
 	rte_pmd_i40e_reset_vf_stats;
 	rte_pmd_i40e_set_tx_loopback;
 	rte_pmd_i40e_set_vf_broadcast;
-- 
2.9.3

  parent reply	other threads:[~2017-04-07  2:34 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-04  1:55 [PATCH v7 0/3] net/i40e: configurable PTYPE mapping Qi Zhang
2017-04-04  1:55 ` [PATCH v7 1/3] net/i40e: enable per dev PTYPE mapping table Qi Zhang
2017-04-04  1:55 ` [PATCH v7 2/3] net/i40e: configurable PTYPE mapping Qi Zhang
2017-04-04  1:55 ` [PATCH v7 3/3] app/testpmd: add CL for ptype mapping configure Qi Zhang
2017-04-04  9:30 ` [PATCH v7 0/3] net/i40e: configurable PTYPE mapping Ferruh Yigit
2017-04-04 20:22   ` Thomas Monjalon
2017-04-05  5:45     ` Jianbo Liu
2017-04-05  6:01       ` Zhang, Qi Z
2017-04-07  3:25 ` [PATCH v8 " Qi Zhang
2017-04-07  3:25   ` [PATCH v8 1/3] net/i40e: enable per dev PTYPE mapping table Qi Zhang
2017-04-07  2:36     ` Zhang, Qi Z
2017-04-12  2:13       ` Zhang, Qi Z
2017-04-07  3:25   ` Qi Zhang [this message]
2017-04-12  8:36     ` [PATCH v8 2/3] net/i40e: configurable PTYPE mapping Ferruh Yigit
2017-04-07  3:25   ` [PATCH v8 3/3] app/testpmd: add CL for ptype mapping configure Qi Zhang
2017-04-12 13:55   ` [PATCH v9 0/3] net/i40e: configurable PTYPE mapping Qi Zhang
2017-04-12 13:55     ` [PATCH v9 1/3] net/i40e: enable per dev PTYPE mapping table Qi Zhang
2017-04-12 13:55     ` [PATCH v9 2/3] net/i40e: configurable PTYPE mapping Qi Zhang
2017-04-12 13:55     ` [PATCH v9 3/3] app/testpmd: add CL for ptype mapping configure Qi Zhang
2017-04-13  9:50     ` [PATCH v9 0/3] net/i40e: configurable PTYPE mapping Chao Zhu
2017-04-13 10:46       ` Ferruh Yigit

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