[Qemu-devel] [PATCH v2 0/3] Enable MTTCG on PPC64

From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, alex.bennee@linaro.org,
	programmingkidx@gmail.com, bharata@linux.vnet.ibm.com,
	nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v2 0/3] Enable MTTCG on PPC64
Date: Fri,  7 Apr 2017 11:37:49 +0530	[thread overview]
Message-ID: <20170407060752.31313-1-nikunj@linux.vnet.ibm.com> (raw)

The series enables Multi-Threaded TCG on PPC64

Patch 01: Use atomic_cmpxchg in store conditional
      02: Handle first write to page during atomic operation
      03: Generate memory barriers for sync/isync and load/store conditional

Patches are based on ppc-for-2.10

Changelog:
v1:
* Rewrote store_conditional as suggested by Richard

Tested using following:
./ppc64-softmmu/qemu-system-ppc64 -cpu POWER8 -vga none -nographic -machine pseries,usb=off -m 2G  -smp 8,cores=8,threads=1 -accel tcg,thread=multi  f23.img

Todo:
* Implement lqarx and stqcx
* Enable other machine types and PPC32.
* More testing for corner cases.

Nikunj A Dadhania (3):
  target/ppc: Emulate LL/SC using cmpxchg helpers
  cputlb: handle first atomic write to the page
  target/ppc: Generate fence operations

 cputlb.c               |  8 +++++++-
 target/ppc/translate.c | 37 +++++++++++++++++++++++++++++++------
 2 files changed, 38 insertions(+), 7 deletions(-)

-- 
2.9.3