From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754817AbdDKMaB (ORCPT ); Tue, 11 Apr 2017 08:30:01 -0400 Received: from foss.arm.com ([217.140.101.70]:59872 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753282AbdDKM34 (ORCPT ); Tue, 11 Apr 2017 08:29:56 -0400 From: Lorenzo Pieralisi To: linux-pci@vger.kernel.org Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Lorenzo Pieralisi , Bjorn Helgaas Subject: [PATCH v3 12/32] m32r: include default ioremap_nopost() implementation Date: Tue, 11 Apr 2017 13:28:52 +0100 Message-Id: <20170411122923.6285-13-lorenzo.pieralisi@arm.com> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") mandate non-posted configuration transactions. As further highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative configuration mechanism, the memory mapped transactions from the host CPU into Configuration Requests on the PCI express fabric may create ordering problems for software because writes to memory address are typically posted transactions (unless the architecture can enforce through virtual address mapping non-posted write transactions behaviour) but writes to Configuration Space are not posted on the PCI express fabric. Include the asm-generic ioremap_nopost() implementation (currently falling back to ioremap_nocache()) to provide a non-posted writes ioremap interface to kernel subsystems. Signed-off-by: Lorenzo Pieralisi Cc: Bjorn Helgaas --- arch/m32r/include/asm/io.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/m32r/include/asm/io.h b/arch/m32r/include/asm/io.h index 4b0f5e0..1577102 100644 --- a/arch/m32r/include/asm/io.h +++ b/arch/m32r/include/asm/io.h @@ -70,6 +70,7 @@ extern void iounmap(volatile void __iomem *addr); #define ioremap_wc ioremap_nocache #define ioremap_wt ioremap_nocache #define ioremap_uc ioremap_nocache +#include /* * IO bus memory addresses are also 1:1 with the physical address -- 2.10.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: lorenzo.pieralisi@arm.com (Lorenzo Pieralisi) Date: Tue, 11 Apr 2017 13:28:52 +0100 Subject: [PATCH v3 12/32] m32r: include default ioremap_nopost() implementation In-Reply-To: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> Message-ID: <20170411122923.6285-13-lorenzo.pieralisi@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") mandate non-posted configuration transactions. As further highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative configuration mechanism, the memory mapped transactions from the host CPU into Configuration Requests on the PCI express fabric may create ordering problems for software because writes to memory address are typically posted transactions (unless the architecture can enforce through virtual address mapping non-posted write transactions behaviour) but writes to Configuration Space are not posted on the PCI express fabric. Include the asm-generic ioremap_nopost() implementation (currently falling back to ioremap_nocache()) to provide a non-posted writes ioremap interface to kernel subsystems. Signed-off-by: Lorenzo Pieralisi Cc: Bjorn Helgaas --- arch/m32r/include/asm/io.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/m32r/include/asm/io.h b/arch/m32r/include/asm/io.h index 4b0f5e0..1577102 100644 --- a/arch/m32r/include/asm/io.h +++ b/arch/m32r/include/asm/io.h @@ -70,6 +70,7 @@ extern void iounmap(volatile void __iomem *addr); #define ioremap_wc ioremap_nocache #define ioremap_wt ioremap_nocache #define ioremap_uc ioremap_nocache +#include /* * IO bus memory addresses are also 1:1 with the physical address -- 2.10.0