From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752868AbdDKMe4 (ORCPT ); Tue, 11 Apr 2017 08:34:56 -0400 Received: from foss.arm.com ([217.140.101.70]:59886 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754793AbdDKM36 (ORCPT ); Tue, 11 Apr 2017 08:29:58 -0400 From: Lorenzo Pieralisi To: linux-pci@vger.kernel.org Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Lorenzo Pieralisi , Bjorn Helgaas , Geert Uytterhoeven Subject: [PATCH v3 13/32] m68k: include default ioremap_nopost() implementation Date: Tue, 11 Apr 2017 13:28:53 +0100 Message-Id: <20170411122923.6285-14-lorenzo.pieralisi@arm.com> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") mandate non-posted configuration transactions. As further highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative configuration mechanism, the memory mapped transactions from the host CPU into Configuration Requests on the PCI express fabric may create ordering problems for software because writes to memory address are typically posted transactions (unless the architecture can enforce through virtual address mapping non-posted write transactions behaviour) but writes to Configuration Space are not posted on the PCI express fabric. Include the asm-generic ioremap_nopost() implementation (currently falling back to ioremap_nocache()) to provide a non-posted writes ioremap interface to kernel subsystems. Signed-off-by: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Geert Uytterhoeven --- arch/m68k/include/asm/io.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h index bccd5a9..ce39ee5 100644 --- a/arch/m68k/include/asm/io.h +++ b/arch/m68k/include/asm/io.h @@ -3,6 +3,7 @@ #else #include #endif +#include #define readb_relaxed(addr) readb(addr) #define readw_relaxed(addr) readw(addr) -- 2.10.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: From: Lorenzo Pieralisi To: linux-pci@vger.kernel.org Subject: [PATCH v3 13/32] m68k: include default ioremap_nopost() implementation Date: Tue, 11 Apr 2017 13:28:53 +0100 Message-Id: <20170411122923.6285-14-lorenzo.pieralisi@arm.com> In-Reply-To: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Lorenzo Pieralisi , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Bjorn Helgaas , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") mandate non-posted configuration transactions. As further highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative configuration mechanism, the memory mapped transactions from the host CPU into Configuration Requests on the PCI express fabric may create ordering problems for software because writes to memory address are typically posted transactions (unless the architecture can enforce through virtual address mapping non-posted write transactions behaviour) but writes to Configuration Space are not posted on the PCI express fabric. Include the asm-generic ioremap_nopost() implementation (currently falling back to ioremap_nocache()) to provide a non-posted writes ioremap interface to kernel subsystems. Signed-off-by: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Geert Uytterhoeven --- arch/m68k/include/asm/io.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h index bccd5a9..ce39ee5 100644 --- a/arch/m68k/include/asm/io.h +++ b/arch/m68k/include/asm/io.h @@ -3,6 +3,7 @@ #else #include #endif +#include #define readb_relaxed(addr) readb(addr) #define readw_relaxed(addr) readw(addr) -- 2.10.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lorenzo Pieralisi Subject: [PATCH v3 13/32] m68k: include default ioremap_nopost() implementation Date: Tue, 11 Apr 2017 13:28:53 +0100 Message-ID: <20170411122923.6285-14-lorenzo.pieralisi@arm.com> References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: linux-pci@vger.kernel.org Cc: linux-arch@vger.kernel.org, Lorenzo Pieralisi , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Bjorn Helgaas , linux-arm-kernel@lists.infradead.org List-Id: linux-arch.vger.kernel.org The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") mandate non-posted configuration transactions. As further highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative configuration mechanism, the memory mapped transactions from the host CPU into Configuration Requests on the PCI express fabric may create ordering problems for software because writes to memory address are typically posted transactions (unless the architecture can enforce through virtual address mapping non-posted write transactions behaviour) but writes to Configuration Space are not posted on the PCI express fabric. Include the asm-generic ioremap_nopost() implementation (currently falling back to ioremap_nocache()) to provide a non-posted writes ioremap interface to kernel subsystems. Signed-off-by: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Geert Uytterhoeven --- arch/m68k/include/asm/io.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h index bccd5a9..ce39ee5 100644 --- a/arch/m68k/include/asm/io.h +++ b/arch/m68k/include/asm/io.h @@ -3,6 +3,7 @@ #else #include #endif +#include #define readb_relaxed(addr) readb(addr) #define readw_relaxed(addr) readw(addr) -- 2.10.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: lorenzo.pieralisi@arm.com (Lorenzo Pieralisi) Date: Tue, 11 Apr 2017 13:28:53 +0100 Subject: [PATCH v3 13/32] m68k: include default ioremap_nopost() implementation In-Reply-To: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> Message-ID: <20170411122923.6285-14-lorenzo.pieralisi@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") mandate non-posted configuration transactions. As further highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative configuration mechanism, the memory mapped transactions from the host CPU into Configuration Requests on the PCI express fabric may create ordering problems for software because writes to memory address are typically posted transactions (unless the architecture can enforce through virtual address mapping non-posted write transactions behaviour) but writes to Configuration Space are not posted on the PCI express fabric. Include the asm-generic ioremap_nopost() implementation (currently falling back to ioremap_nocache()) to provide a non-posted writes ioremap interface to kernel subsystems. Signed-off-by: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Geert Uytterhoeven --- arch/m68k/include/asm/io.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h index bccd5a9..ce39ee5 100644 --- a/arch/m68k/include/asm/io.h +++ b/arch/m68k/include/asm/io.h @@ -3,6 +3,7 @@ #else #include #endif +#include #define readb_relaxed(addr) readb(addr) #define readw_relaxed(addr) readw(addr) -- 2.10.0